參數(shù)資料
型號： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 35/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
12
06/04/02 Revision 1.07
4.1
Types of Transactions
This section provides a summary of PCI transactions performed by PI7C7300.
Table 4–1 lists the command code and name of each PCI transaction. The Master and
Target columns indicate support for each transaction when PI7C7300 initiates
transactions as a master, on the primary (P) and secondary (S1, S2) buses, and when
PI7C7300 responds to transactions as a target, on the primary (P) and secondary (S1,
S2) buses.
TABLE 4-1. PCI TRANSACTIONS
Types of Transactions
Initiates as Master
Responds as Target
Primary
Secondary
Primary
Secondary
0000
Interrupt Acknowledge
N
0001
Special Cycle
Y
N
0010
I/O Read
Y
0011
I/O Write
Y
0100
Reserved
N
0101
Reserved
N
0110
Memory Read
Y
0111
Memory Write
Y
1000
Reserved
N
1001
Reserved
N
1010
Configuration Read
N
Y
N
1011
Configuration Write
Y (Type 1 only)
Y
Y (Type 1 only)
1100
Memory Read Multiple
Y
1101
Dual Address Cycle
Y
1110
Memory Read Line
Y
1111
Memory Write and Invalidate
Y
As indicated in Table 4–1, the following PCI commands are not supported by
PI7C7300:
§
PI7C7300 never initiates a PCI transaction with a reserved command code and, as
a target, PI7C7300 ignores reserved command codes.
§
PI7C7300 does not generate interrupt acknowledge transactions. PI7C7300
ignores interrupt acknowledge transactions as a target.
§
PI7C7300 does not respond to special cycle transactions. PI7C7300 cannot
guarantee delivery of a special cycle transaction to downstream buses because of
the broadcast nature of the special cycle command and the inability to control the
transaction as a target. To generate special cycle transactions on other PCI buses,
either upstream or downstream, Type 1 configuration write must be used.
§
PI7C7300 neither generates Type 0 configuration transactions on the primary PCI
bus nor responds to Type 0 configuration transactions on the secondary PCI
buses.
4.2
Single Address Phase
A 32-bit address uses a single address phase. This address is driven on P_AD[31:0],
and the bus command is driven on P_CBE[3:0]. PI7C7300 supports the linear
increment address mode only, which is indicated when the lowest two address bits are
equal to zero. If either of the lowest two address bits is nonzero, PI7C7300
automatically disconnects the transaction after the first data transfer.
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