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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 87/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
vii
06/04/02 Revision 1.07
5
ADDRESS DECODING...................................................................................................................31
5.1
ADDRESS RANGES .....................................................................................................................31
5.2
I/O ADDRESS DECODING ............................................................................................................31
5.2.1
I/O Base and Limit Address Register................................................................................32
5.2.2
ISA Mode ..........................................................................................................................33
5.3
MEMORY ADDRESS DECODING ...................................................................................................33
5.3.1
Memory-Mapped I/O Base and Limit Address Registers..................................................34
5.3.2
Prefetchable Memory Base and Limit Address Registers.................................................35
5.4
VGA SUPPORT ..........................................................................................................................36
5.4.1
VGA Mode.........................................................................................................................36
5.4.2
VGA Snoop Mode .............................................................................................................36
6
TRANSACTION ORDERING ..........................................................................................................37
6.1
TRANSACTIONS GOVERNED BY ORDERING RULES .......................................................................37
6.2
GENERAL ORDERING GUIDELINES...............................................................................................38
6.3
ORDERING RULES ......................................................................................................................38
6.4
DATA SYNCHRONIZATION............................................................................................................40
7
ERROR HANDLING........................................................................................................................40
7.1
ADDRESS PARITY ERRORS .........................................................................................................40
7.2
DATA PARITY ERRORS................................................................................................................41
7.2.1
Configuration Write Transactions to Configuration Space ................................................41
7.2.2
Read Transactions............................................................................................................42
7.2.3
Delayed Write Transactions..............................................................................................43
7.2.4
Posted Write Transactions................................................................................................45
7.3
DATA PARITY ERROR REPORTING SUMMARY...............................................................................46
7.4
SYSTEM ERROR (SERR#) REPORTING .......................................................................................50
8
EXCLUSIVE ACCESS ....................................................................................................................51
8.1
CONCURRENT LOCKS .................................................................................................................51
8.2
ACQUIRING EXCLUSIVE ACCESS ACROSS PI7C7300 ...................................................................51
8.2.1
Locked Transactions in Downstream Direction.................................................................51
8.2.2
Locked Transaction in Upstream Direction .......................................................................53
8.3
ENDING EXCLUSIVE ACCESS.......................................................................................................53
9
PCI BUS ARBITRATION ................................................................................................................54
9.1
PRIMARY PCI BUS ARBITRATION.................................................................................................54
9.2
SECONDARY PCI BUS ARBITRATION ...........................................................................................54
9.2.1
Secondary Bus Arbitration Using the Internal Arbiter .......................................................54
9.2.2
Preemption........................................................................................................................56
9.2.3
Secondary Bus Arbitration Using An External Arbiter.......................................................56
9.2.4
Bus Parking.......................................................................................................................56
10
COMPACT PCI HOT SWAP .......................................................................................................57
11
CLOCKS......................................................................................................................................57
11.1 PRIMARY CLOCK INPUTS.............................................................................................................57
11.2 SECONDARY CLOCK OUTPUTS ....................................................................................................57
12
RESET .........................................................................................................................................58
12.1 PRIMARY INTERFACE RESET .......................................................................................................58
12.2 SECONDARY INTERFACE RESET ..................................................................................................58
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相關代理商/技術參數(shù) |
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| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
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