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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 113/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
83
06/04/02 Revision 1.07
15.1
Bridge Actions for Various Cycle Types (continued)
Initiator
Target
Response
Master on Secondary
Target on Primary or the
other Secondary Port
PI7C7300 asserts S1_DEVSEL# or
S2_DEVSEL#, terminates the cycle
normally if it is able to be posted,
otherwise returns with a retry. It then
passes the cycle to the appropriate
port. When cycle is complete on the
target port, it will wait for the initiator
to repeat the same cycle and end with
normal termination.
Master on Secondary
Target not on Primary nor
the other Secondary Port
PI7C7300 does not respond.
15.2
Transaction Ordering
To maintain data coherency and consistency, PI7C7300 complies with the ordering
rules put forth in the PCI Local Bus Specification, Rev 2.2. The following table
summarizes the ordering relationship of all the transactions through the bridge.
PMW - Posted write (either memory write or memory write & invalidate)
DRR - Delayed read request (all memory read, I/O read & configuration read)
DWR - Delayed write request (I/O write & configuration write, memory write to
certain location)
DRC - Delayed read completion (all memory read, I/O read & configuration read)
DWC - Delayed write completion (I/O write & configuration write, memory write
to ccertain location
Cycle type shown on each row is the subsequent cycle after the previous shown on the
column.
Can Row Pass Column?
PMW
Column 1
DRR
Column 2
DWR
Column 3
DRC
Column 4
DWC
Column 5
PMW (Row 1)
No
Yes
DRR (Row 2)
No
Yes
DWR (Row 3)
No
Yes
DRC (Row 4)
No
Yes
No
DWC (Row 5)
Yes
No
In Row 1 Column 1, PMW cannot pass the previous PMW and that means they must
complete on the target bus in the order in which they were received in the initiator bus.
In Row 2 Column1,DRR cannot pass the previous PMW and that means the previous
PMW heading to the same direction must be completed before the DRR can be
attempted on the target bus.
In Row 1 Column 2, PMW can pass the previous DRR as long as the DRR reaches
the head of the delayed transaction queue.
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