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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 13/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
1
06/04/02 Revision 1.07
1
Introduction
Product Description
The PI7C7300 is Pericom Semiconductor’s second-generation PCI-PCI Bridge.
It is designed to be fully compliant with the 32-bit, 66MHz implementation of
the PCI Local Bus Specification, Revision 2.2.
The PI7C7300 supports only
synchronous bus transactions between devices on the Primary Bus running at 33MHz
to 66MHz and the Secondary Buses operating at either 33MHz or 66MHz. The
Primary and Secondary Buses can also operate in concurrent mode, resulting in added
increase in system performance. Concurrent bus operation off-loads and isolates
unnecessary traffic from the Primary Bus; thereby enabling a master and a target
device on the same Secondary PCI Bus to communicate even while the Primary Bus is
busy. In addition, the Secondary Buses have load balancing capability, allowing faster
devices to be isolated away from slower devices. Among the other features supported
by the PI7C7300 are: support for up to 15 devices on the Secondary Buses, Compact
PCI Hot Swap (PICMG 2.1, R1.0) Friendly Support and Dual Addressing Cycle.
Product Feature
32-bit Primary and Two Secondary Ports run up to 66MHz
All 3 ports compliant with the PCI Local Bus Specification, Revision 2.2
Compliant with PCI-to-PCI Bridge Architecture Specification, Revision 1.1.
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All I/O and memory commands
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Type 1 to Type 0 configuration conversion
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Type 1 to Type 1 configuration forwarding
-
Type 1 configuration write to special cycle conversion
Concurrent Primary to Secondary Bus operation and independent intra-Secondary
Port channel to reduce traffic on the Primary Port
Provides internal arbitration for one set of eight secondary bus masters (S1 bus)
and one set of seven (eight if Hot Swap is disable)secondary bus masters (S2 bus)
-
Programmable 2-level priority arbiter
-
Disable control for use of external arbiter
Supports posted write buffers in all directions
Three 128 byte FIFO’s for delay transactions
Three 128 byte FIFO’s for posted memory transactions
Enhanced address decoding
-
32-bit I/O address range
-
32-bit memory-mapped I/O address range
-
VGA addressing and VGA palette snooping
-
ISA-aware mode for legacy support in the first 64KB of I/O address range
Dual Addressing cycle (64-bit)
Interrupt handling
-
PCI interrupts are routed through an external interrupt concentrator
Supports system transaction ordering rules
Tri-state control of output buffers on secondary buses
Compact PCI Hot Swap (PICMG 2.1, R1.0) Friendly Support
Industrial Temperature range –40°C to 85°C
IEEE 1149.1 JTAG interface support
3.3V core; 3.3V PCI I/O interface with 5V I/O tolerance
272-pin plastic BGA package
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