參數(shù)資料
型號: PI7C7300NA
廠商: PERICOM SEMICONDUCTOR CORP
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA272
封裝: PLASTIC, BGA-272
文件頁數(shù): 97/119頁
文件大?。?/td> 880K
代理商: PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
69
06/04/02 Revision 1.07
14.1.19
Prefetchable Memory Base Register – Offset 24h
Bit
Function
Type
Description
3:0
64-bit
addressing
R/O
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
15:4
Prefetchable
Memory Base
Address [31:20]
R/W
Defines the bottom address of an address range for the bridge
to determine when to forward memory read and write
transactions from one interface to the other. The upper 12 bits
correspond to address bits [31:20] and are writable. The lower
20 bits are assumed to be 0.
14.1.20
Prefetchable Memory Limit Register – Offset 24h
Bit
Function
Type
Description
19:16
64-bit
addressing
R/O
Indicates 64-bit addressing
0000: 32-bit addressing
0001: 64-bit addressing
Reset to 1
31:20
Prefetchable
Memory Base
Address [31:20]
R/W
Defines the top address of an address range for the bridge to
determine when to forward memory read and write
transactions from one interface to the other. The upper 12 bits
correspond to address bits [31:20] and are writable. The lower
20 bits are assumed to be FFFFFh.
14.1.21
Prefetchable Memory Base Address Upper 32-bits Register –
Offset 28h
Bit
Function
Type
Description
31:0
Prefetchable
Memory Base
Address, Upper
32-bits [63:32]
R/W
Defines the upper 32-bits of a 64-bit bottom address of an
address range for the bridge to determine when to forward
memory read and write transactions from one interface to the
other.
Reset to 0
14.1.22
Prefetchable Memory Limit Address Upper 32-bits Register
– Offset 2Ch
Bit
Function
Type
Description
31:0
Prefetchable
Memory Limit
Address, Upper
32-bits [63:32]
R/W
Defines the upper 32-bits of a 64-bit top address of an address
range for the bridge to determine when to forward memory
read and write transactions from one interface to the other.
Reset to 0
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