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參數(shù)資料
| 型號(hào)： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 80/119頁(yè) |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
53
06/04/02 Revision 1.07
- I/O Write induces master abort
- Memory Write induces master abort
When PI7C7300 receives a target abort or a master abort in response to the delayed
locked read transaction, this status is passed back to the initiator, and no locks are
established on either the target or the initiator bus. PI7C7300 resumes forwarding
unlocked transactions in both directions.
8.2.2
Locked Transaction in Upstream Direction
PI7C7300 ignores upstream lock and transactions. PI7C7300 will pass these
transactions as normal transactions without lock established.
8.3
Ending Exclusive Access
After the lock has been acquired on both initiator and target buses, PI7C7300 must
maintain the lock on the target bus for any subsequent locked transactions until the
initiator relinquishes the lock.
The only time a target-retry causes the lock to be relinquished is on the first
transaction of a locked sequence. On subsequent transactions in the sequence,
the target retry has no effect on the status of the lock signal.
An established target lock is maintained until the initiator relinquishes the lock.
PI7C7300 does not know whether the current transaction is the last one in a sequence
of locked transactions until the initiator de-asserts the LOCK# signal at
end of the transaction.
When the last locked transaction is a delayed transaction, PI7C7300 has already
completed the transaction on the target bus. In this example, as soon as PI7C7300
detects that the initiator has relinquished the LOCK# signal by sampling it in the de-
asserted state while FRAME# is de-asserted, PI7C7300 de-asserts the LOCK# signal
on the target bus as soon as possible. Because of this behavior, LOCK# may not be
de-asserted until several cycles after the last locked transaction has been completed
on the target bus. As soon as PI7C7300 has de-asserted LOCK# to indicate the end of
a sequence of locked transactions, it resumes forwarding unlocked transactions.
When the last locked transaction is a posted write transaction, PI7C7300 de-asserts
LOCK# on the target bus at the end of the transaction because the lock was
relinquished at the end of the write transaction on the initiator bus.
When PI7C7300 receives a target abort or a master abort in response to a locked
delayed transaction, PI7C7300 returns a target abort or a master abort when the
initiator repeats the locked transaction. The initiator must then de-assert LOCK# at the
end of the transaction. PI7C7300 sets the appropriate status bits, flagging the
abnormal target termination condition (see Section 4.8). Normal forwarding of
unlocked posted and delayed transactions is resumed.
When PI7C7300 receives a target abort or a master abort in response to a locked
posted write transaction, PI7C7300 cannot pass back that status to the initiator.
PI7C7300 asserts SERR# on the initiator bus when a target abort or a master abort
is received during a locked posted write transaction, if the SERR# enable bit is set in
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