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參數(shù)資料
| 型號(hào)： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 117/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
87
06/04/02 Revision 1.07
TABLE 16-1. TAP PINS (CONTINUED)
Instruction
/
Requisite
Opcode (binary)
Description
Sample/preload
IEEE 1149.1
Required
0001
Sample/preload performs two functions:
§
A snapshot of the sample instruction is captured on
the rising edge of TCK without interfering with normal
operation. The instruction causes boundary-scan
register cells associated with outputs to sample the
value being driven.
§
On the falling edge of TCK, the data held in the
boundary-scan cells is transferred to the slave
register cells. Typically, the slave latched data is
applied to the system outputs via the extest
instruction.
Idcode
IEEE 1149.1
Required
0101
Reserved
Bypass
IEEE 1149.1
Required
1111
Bypass instruction selects the one-bit bypass register
between TDI and TDO pins. 0 (binary) is the only
instruction that accesses the bypass register. While this
instruction is in effect, all other test data registers have no
effect on system operation. Test data registers with both
test and system functionality perform their system
functions when this instruction is selected.
16.3
TAP Test Data Registers
The PI7C7300 contains two test data registers (bypass and boundary-scan).
Each test data register selected by the TAP controller is connected serially between
TDI and TDO. TDI is connected to the test data register’s most significant bit.
TDO is connected to the least significant bit. Data is shifted one bit position within the
register towards TDO on each rising edge of TCK. While any register is selected, data
is transferred from TDI to TDO without inversion. The following sections describe each
of the test data registers.
16.4
Bypass Register
The required bypass register, a one-bit shift register, provides the shortest path
between TDI and TDO when a bypass instruction is in effect. This allows rapid
movement of test data to and from other components on the board. This path
can be selected when no test operation is being performed on the PI7C7300.
16.5
Boundary-Scan Register
The boundary-scan register contains a cell for each pin as well as control cells for I/O
and the high-impedance pin.
Table 15-2 shows the bit order of the PI7C7300 boundary-scan register. All table cells
that contain “Control” select the direction of bi-directional pins or high-impedance
output pins. When a “0” is loaded into the control cell, the associated pin(s) are high-
impedance or selected as input.
The boundary-scan register is a required set of serial-shiftable register cells,
configured in master/slave stages and connected between each of the PI7C7300’s
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