參數(shù)資料
型號： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 53/119頁
文件大小： 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
29
06/04/02 Revision 1.07
§
PI7C7300 makes 2
24 (default) read attempts resulting in a response of target retry.
TABLE 4-9. RESPONSE TO DELAYED READ TARGET TERMINATION
Target Termination
Response
Normal
If prefetchable, target disconnect only if initiator requests more data than
read from target. If non-prefetchable, target disconnect on first data
phase.
Target Retry
Re-initiate read transaction to target
Target Disconnect
If initiator requests more data than read from target, return target
disconnect to initiator.
Target Abort
Return target abort to initiator. Set received target abort bit in the target
interface status register. Set signaled target abort bit in the initiator
interface status register.
After PI7C7300 makes 2
24(default) attempts of the same delayed read transaction on
the target bus, PI7C7300 asserts P_SERR# if the primary SERR# enable bit is set (bit
8 of command register for secondary bus S1 or S2) and the delayed-write-non-delivery
bit is not set. The delayed-write-non-delivery bit is bit 5 of P_SERR# event disable
register (offset 64h). PI7C7300 will report system error. See Section 7.4 for a
description of system error conditions.
4.9.4
Target Termination Initiated by PI7C7300
PI7C7300 can return a target retry, target disconnect, or target abort to an initiator for
reasons other than detection of that condition at the target interface.
4.9.4.1
Target Retry
PI7C7300 returns a target retry to the initiator when it cannot accept write data or
return read data as a result of internal conditions. PI7C7300 returns a target retry to an
initiator when any of the following conditions is met:
For delayed write transactions:
§
The transaction is being entered into the delayed transaction queue.
§
Transaction has already been entered into delayed transaction queue, but target
response has not yet been received.
§
Target response has been received but has not progressed to the head of the
return queue.
§
The delayed transaction queue is full, and the transaction cannot be queued.
§
A transaction with the same address and command has been queued.
§
A locked sequence is being propagated across PI7C7300, and the write
transaction is not a locked transaction.
§
The target bus is locked and the write transaction is a locked transaction.
§
Use more than 16 clocks to accept this transaction.
For delayed read transactions:
§
The transaction is being entered into the delayed transaction queue.
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