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參數(shù)資料
| 型號(hào)： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 68/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
42
06/04/02 Revision 1.07
§
PI7C7300 sets the detected parity error bit in the status register, regardless of the
state of the parity error response bit.
7.2.2
Read Transactions
When PI7C7300 detects a parity error during a read transaction, the target drives data
and data parity, and the initiator checks parity and conditionally asserts PERR#.
For downstream transactions, when PI7C7300 detects a read data parity error on the
secondary bus, the following events occur:
§
PI7C7300 asserts S_PERR# two cycles following the data transfer, if the
secondary interface parity error response bit is set in the bridge control register.
§
PI7C7300 sets the detected parity error bit in the secondary status register.
§
PI7C7300 sets the data parity detected bit in the secondary status register, if the
secondary interface parity error response bit is set in the bridge control register.
§
PI7C7300 forwards the bad parity with the data back to the initiator on the primary
bus. If the data with the bad parity is pre-fetched and is not read by the initiator on
the primary bus, the data is discarded and the data with bad parity is not returned
to the initiator.
§
PI7C7300 completes the transaction normally.
For upstream transactions, when PI7C7300 detects a read data parity error on the
primary bus, the following events occur:
§
PI7C7300 asserts P_PERR# two cycles following the data transfer, if the primary
interface parity error response bit is set in the command register.
§
PI7C7300 sets the detected parity error bit in the primary status register.
§
PI7C7300 sets the data parity detected bit in the primary status register, if the
primary interface parity-error-response bit is set in the command register.
§
PI7C7300 forwards the bad parity with the data back to the initiator on the
secondary bus. If the data with the bad parity is pre-fetched and is not read by the
initiator on the secondary bus, the data is discarded and the data with bad parity is
not returned to the initiator.
§
PI7C7300 completes the transaction normally.
PI7C7300 returns to the initiator the data and parity that was received from the target.
When the initiator detects a parity error on this read data and is enabled to report it, the
initiator asserts PERR# two cycles after the data transfer occurs. It is assumed that the
initiator takes responsibility for handling a parity error condition; therefore, when
PI7C7300 detects PERR# asserted while returning read data to the initiator, PI7C7300
does not take any further action and completes the transaction normally.
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