參數(shù)資料
型號(hào)： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 77/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
50
06/04/02 Revision 1.07
§
The parity error response bit on the command register and the parity error
response bit on the bridge control register must both be set.
§
The SERR# enable bit must be set in the command register.
TABLE 7-7. ASSERTION OF P_SERR# FOR DATA PARITY ERRORS
P_SERR#
Transaction
Type
Direction
Bus Where
Error Was
Detected
Primary /
Secondary
Parity Error
Response Bits
1 (de-asserted)
Read
Downstream
Primary
x / x
1
Read
Downstream
Secondary
x / x
1
Read
Upstream
Primary
x / x
1
Read
Upstream
Secondary
x / x
1
Posted Write
Downstream
Primary
x / x
0
2 (asserted)
Posted Write
Downstream
Secondary
1 / 1
0
3
Posted Write
Upstream
Primary
1 / 1
1
Posted Write
Upstream
Secondary
x / x
1
Delayed Write
Downstream
Primary
x / x
1
Delayed Write
Downstream
Secondary
x / x
1
Delayed Write
Upstream
Primary
x / x
1
Delayed Write
Upstream
Secondary
x / x
X = don’t care
2
The parity error was detected on the target (secondary) bus but not on the initiator (primary) bus.
3
The parity error was detected on the target (primary) bus but not on the initiator (secondary) bus.
7.4
System Error (SERR#) Reporting
PI7C7300 uses the P_SERR# signal to report conditionally a number of system error
conditions in addition to the special case parity error conditions described in Section
7.2.3.
Whenever assertion of P_SERR# is discussed in this document, it is assumed that the
following conditions apply:
§
For PI7C7300 to assert P_SERR# for any reason, the SERR# enable bit must be
set in the command register.
§
Whenever PI7C7300 asserts P_SERR#, PI7C7300 must also set the signaled
system error bit in the status register.
In compliance with the PCI-to-PCI Bridge Architecture Specification, PI7C7300 asserts
P_SERR# when it detects the secondary SERR# input, S_SERR#, asserted and the
SERR# forward enable bit is set in the bridge control register. In addition, PI7C7300
also sets the received system error bit in the secondary status register.
PI7C7300 also conditionally asserts P_SERR# for any of the following reasons:
§
Target abort detected during posted write transaction
§
Master abort detected during posted write transaction
§
Posted write data discarded after 2
24 (default) attempts to deliver (224 target retries
received)
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