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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 69/119頁 |
| 文件大小： | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
43
06/04/02 Revision 1.07
7.2.3
Delayed Write Transactions
When PI7C7300 detects a data parity error during a delayed write transaction, the
initiator drives data and data parity, and the target checks parity and conditionally
asserts PERR#.
For delayed write transactions, a parity error can occur at the following times:
§
During the original delayed write request transaction
§
When the initiator repeats the delayed write request transaction
§
When PI7C7300 completes the delayed write transaction to the target
When a delayed write transaction is normally queued, the address, command, address
parity, data, byte enable bits, and data parity are all captured and a target retry is
returned to the initiator. When PI7C7300 detects a parity error on the write data for the
initial delayed write request transaction, the following events occur:
§
If the parity-error-response bit corresponding to the initiator bus is set, PI7C7300
asserts TRDY# to the initiator and the transaction is not queued. If multiple data
phases are requested, STOP# is also asserted to cause a target disconnect. Two
cycles after the data transfer, PI7C7300 also asserts PERR#.
If the parity-error-response bit is not set, PI7C7300 returns a target retry.
It queues the transaction as usual. PI7C7300 does not assert PERR#.
In this case, the initiator repeats the transaction.
§
PI7C7300 sets the detected-parity-error bit in the status register corresponding to
the initiator bus, regardless of the state of the parity-error-response bit.
Note: If parity checking is turned off and data parity errors have occurred for queued
or subsequent delayed write transactions on the initiator bus, it is possible that the
initiator’s re-attempts of the write transaction may not match the original queued
delayed write information contained in the delayed transaction queue. In this case, a
master timeout condition may occur, possibly resulting in a system error (P_SERR#
assertion).
For downstream transactions, when PI7C7300 is delivering data to the target on the
secondary bus and S_PERR# is asserted by the target, the following events occur:
§
PI7C7300 sets the secondary interface data parity detected bit in the secondary
status register, if the secondary parity error response bit is set in the bridge control
register.
§
PI7C7300 captures the parity error condition to forward it back to the initiator on
the primary bus.
Similarly, for upstream transactions, when PI7C7300 is delivering data to the target on
the primary bus and P_PERR# is asserted by the target, the following events occur:
§
PI7C7300 sets the primary interface data-parity-detected bit in the status register,
if the primary parity-error-response bit is set in the command register.
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相關代理商/技術參數(shù) |
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| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
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