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| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 41/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
18
06/04/02 Revision 1.07
Non-prefetchable behavior is used for I/O and configuration read transactions,
as well as for memory read transactions that fall into non-prefetchable memory space.
If extra read transactions could have side effects, for example, when accessing a
FIFO, use non-prefetchable read transactions to those locations. Accordingly, if it is
important to retain the value of the byte enable bits during the data phase, use non-
prefetchable read transactions. If these locations are mapped in memory space, use
the memory read command and map the target into non-prefetchable (memory-
mapped I/O) memory space to use non-prefetching behavior.
4.7.3
Read Prefetch Address Boundaries
PI7C7300 imposes internal read address boundaries on read pre-fetched data.
When a read transaction reaches one of these aligned address boundaries, the
PI7C7300 stops pre-fetched data, unless the target signals a target disconnect before
the read pre-fetched boundary is reached. When PI7C7300 finishes transferring this
read data to the initiator, it returns a target disconnect with the last data transfer,
unless the initiator completes the transaction before all pre-fetched read data is
delivered. Any leftover pre-fetched data is discarded.
Prefetchable read transactions in flow-through mode pre-fetch to the nearest aligned
4KB address boundary, or until the initiator de-asserts FRAME#. Section 4.7.6
describes flow-through mode during read operations.
Table 4-5 shows the read pre-fetch address boundaries for read transactions during
non-flow-through mode.
TABLE 4-4. READ PREFETCH ADDRESS BOUNDARIES
Type of Transaction
Address Space
Cache Line Size
(CLS)
Prefetch Aligned Address
Boundary
Configuration Read
-
*
One DWORD (no prefetch)
I/O Read
-
*
One DWORD (no prefetch)
Memory Read
Non-Prefetchable
*
One DWORD (no prefetch)
Memory Read
Prefetchable
CLS = 0 or 16
16-DWORD aligned address
boundary
Memory Read
Prefetchable
CLS = 1, 2, 4, 8, 16
Cache line address
boundary
Memory Read Line
-
CLS = 0 or 16
16-DWORD aligned address
boundary
Memory Read Line
-
CLS = 1, 2, 4, 8, 16
Cache line boundary
Memory Read Multiple
-
CLS = 0 or 16
32-DWORD aligned address
boundary
Memory Read Multiple
-
CLS = 1, 2, 4, 8, 16
2X of cache line boundary
- does not matter if it is prefetchable or non-prefetchable
* don’t care
TABLE 4-5. READ TRANSACTION PREFETCHING
Type of Transaction
Read Behavior
I/O Read
Prefetching never allowed
Configuration Read
Prefetching never allowed
Downstream: Prefetching used if address is prefetchable space
Memory Read
Upstream: Prefetching used or programmable
Memory Read Line
Prefetching always used
Memory Read Multiple
Prefetching always used
See Section 5.3 for detailed information about prefetchable and non-prefetchable address spaces.
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