參數(shù)資料
型號(hào)： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁(yè)數(shù)： 51/119頁(yè)
文件大?。?/td> 880K
代理商： PI7C7300NA
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
27
06/04/02 Revision 1.07
the master-abort-on-posted-write is not set. The master-abort-on-posted-write bit is bit
4 of the P_SERR# event disable register (offset 64h).
Note: When PI7C7300 performs a Type 1 to special cycle conversion, a master abort
is the expected termination for the special cycle on the target bus. In this case, the
master abort received bit is not set, and the Type 1 configuration transaction is dis-
connected after the first data phase.
4.9.3
Target Termination Received by PI7C7300
When PI7C7300 initiates a transaction on the target bus and the target responds with
DEVSEL#, the target can end the transaction with one of the following types
of termination:
§
Normal termination (upon de-assertion of FRAME#)
§
Target retry
§
Target disconnect
§
Target abort
PI7C7300 handles these terminations in different ways, depending on the type of
transaction being performed.
4.9.3.1
Delayed Write Target Termination Response
When PI7C7300 initiates a delayed write transaction, the type of target termination
received from the target can be passed back to the initiator. Table 4–7 shows the
response to each type of target termination that occurs during a delayed write
transaction.
PI7C7300 repeats a delayed write transaction until one of the following conditions is
met:
§
PI7C7300 completes at least one data transfer.
§
PI7C7300 receives a master abort.
§
PI7C7300 receives a target abort.
PI7C7300 makes 2
24 (default) or 232 (maximum) write attempts resulting in a response
of target retry.
TABLE 4-7. DELAYED WRITE TARGET TERMINATION RESPONSE
Target Termination
Response
Normal
Returning disconnect to initiator with first data transfer only if multiple
data phases requested.
Target Retry
Returning target retry to initiator. Continue write attempts to target
Target Disconnect
Returning disconnect to initiator with first data transfer only if multiple
data phases requested.
Target Abort
Returning target abort to initiator. Set received target abort bit in target
interface status register. Set signaled target abort bit in initiator interface
status register.
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