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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 85/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
58
06/04/02 Revision 1.07
outputs are derived from P_CLK. The secondary clock edges are delayed from P_CLK
edges by a minimum of 0ns. This is the rule for using secondary clocks:
§
Each secondary clock output is limited to no more than one load.
12
Reset
This chapter describes the primary interface, secondary interface, and chip reset
mechanisms.
12.1
Primary Interface Reset
PI7C7300 has a reset input, P_RESET#. When P_RESET# is asserted, the following
events occur:
§
PI7C7300 immediately 3-states all primary and secondary PCI interface signals.
§
PI7C7300 performs a chip reset.
§
Registers that have default values are reset.
P_RESET# asserting and de-asserting edges can be asynchronous to P_CLK and
S_CLK. PI7C7300 is not accessible during P_RESET#. After P_RESET# is de-
asserted, PI7C7300 remains inaccessible for 2
25 PCI clocks (T
rhfa, page 128 of the PCI
Local Bus Specification Rev 2.2) before the first configuration transaction can be
accepted.
12.2
Secondary Interface Reset
PI7C7300 is responsible for driving the secondary bus reset signals, S1_RESET# and
S2_RESET#. PI7C7300 asserts S1_RESET# or S2_RESET# when any of the
following conditions is met:
§
Signal P_RESET# is asserted. Signal S1_RESET# or S2_RESET# remains
asserted as long as P_RESET# is asserted and does not de-assert until
P_RESET# is de-asserted.
§
The secondary reset bit in the bridge control register is set. Signal
S1_RESET# or S2_RESET# remains asserted until a configuration write operation
clears the secondary reset bit.
§
S1_RESET# or S2_RESET# pin is asserted. When S1_RESET# or S2_RESET#
is asserted, PI7C7300 immediately 3-states all the secondary PCI interface signals
associated with the Secondary S1 or S2 port. The S1_RESET# or S2_RESET# in
asserting and de-asserting edges can be asynchronous to P_CLK.
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