參數(shù)資料
型號： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 114/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
84
06/04/02 Revision 1.07
15.3
Abnormal Termination (Initiated by Bridge Master)
15.3.1
Master Abort
Master abort indicates that when PI7C7300 acts as a master and receives no
response (i.e., no target asserts DEVSEL# or S1_DEVSEL# or S2_DEVSEL#) from
a target, the bridge de-asserts FRAME# and then de-asserts IRDY#.
15.3.2
Parity and Error Reporting
Parity must be checked for all addresses and write data. Parity is defined on the
P_PAR, S1_PAR, and S2_PAR signals. Parity should be even (i. e. an even number
of‘1’s) across AD, CBE, and PAR. Parity information on PAR is valid the cycle after AD
and CBE are valid. For reads, even parity must be generated using the initiators CBE
signals combined with the read data. Again, the PAR signal corresponds to read data
from the previous data phase cycle.
15.3.3
Reporting Parity Errors
For all address phases, if a parity error is detected, the error should be reported on the
P_SERR# signal by asserting P_SERR# for one cycle and then 3-stating two cycles
after the bad address. P_SERR# can only be asserted if bit 6 and 8 in the Command
Register are both set to 1. For write data phases, a parity error should be reported by
asserting the P_PERR# signal two cycles after the data phase and should remain
asserted for one cycle when bit 6 in the Command register is set to a 1.
The target reports any type of data parity errors during write cycles, while the master
reports data parity errors during read cycles.
Detection of an address parity error will cause the PCI-to-PCI Bridge target to not claim
the bus (P_DEVSEL# remains inactive) and the cycle will then terminate with a Master
Abort. When the bridge is acting as master, a data parity error during a read cycle
results in the bridge master initiating a Master Abort.
15.3.4
Secondary IDSEL mapping
When PI7C7300 detects a Type 1 configuration transaction for a device connected to
the secondary, it translates the Type 1 transaction to Type 0 transaction on the
downstream interface. Type 1 configuration format uses a 5-bit field at P_AD[15:11] as
a device number. This is translated to S1_AD[31:16] or S2_AD[31:16] by PI7C7300.
16
IEEE 1149.1 Compatible JTAG Controller
An IEEE 1149.1 compatible Test Access Port (TAP) controller and associated TAP
pins are provided to support boundary scan in PI7C7300 for board-level continuity test
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