參數(shù)資料
型號： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 109/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
ix
06/04/02 Revision 1.07
14.1.37
Port Option Register – Offset 74h (continued) ..............................................................78
14.1.38
Master Timeout Counter Register – Offset 74h.............................................................78
14.1.39
Retry Counter Register – Offset 78h .............................................................................78
14.1.40
Sampling Timer Register – Offset 7Ch..........................................................................79
14.1.41
Secondary Successful I/O Read Counter Register – Offset 80h ..................................79
14.1.42
Secondary Successful I/O Write Counter Register – Offset 84h...................................79
14.1.43
Secondary Successful Memory Read Counter Register – Offset 88h ..........................79
14.1.44
Secondary Successful Memory Write Counter Register – Offset 8Ch..........................79
14.1.45
Primary Successful I/O Read Counter Register – Offset 90h .......................................80
14.1.46
Primary Successful I/O Write Counter Register – Offset 94h .......................................80
14.1.47
Primary Successful Memory Read Counter Register – Offset 98h ...............................80
14.1.48
Primary Successful Memory Write Counter Register – Offset 9Ch...............................80
14.1.49
Capability ID Register – Offset B0h...............................................................................80
14.1.50
Next Pointer Register – Offset B0h ...............................................................................81
14.1.51
Slot Number Register – Offset B0h ...............................................................................81
14.1.52
Chassis Number Register – Offset B0h ........................................................................81
14.1.53
Capability ID Register – Offset C0h ..............................................................................81
14.1.54
Next Pointer Register – Offset C0h ...............................................................................81
14.1.55
Hot Swap Control and Status Register – Offset C0h ....................................................82
15
BRIDGE BEHAVIOR ...................................................................................................................82
15.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES ............................................................................82
15.1 BRIDGE ACTIONS FOR VARIOUS CYCLE TYPES (CONTINUED)........................................................83
15.2 TRANSACTION ORDERING ...........................................................................................................83
15.3 ABNORMAL TERMINATION (INITIATED BY BRIDGE MASTER) ...........................................................84
15.3.1
Master Abort......................................................................................................................84
15.3.2
Parity and Error Reporting ................................................................................................84
15.3.3
Reporting Parity Errors .....................................................................................................84
15.3.4
Secondary IDSEL mapping...............................................................................................84
16
IEEE 1149.1 COMPATIBLE JTAG CONTROLLER ...................................................................84
16.1 BOUNDARY SCAN ARCHITECTURE ...............................................................................................85
16.1.1
TAP Pins ...........................................................................................................................85
16.1.2
Instruction Register ...........................................................................................................86
16.2 BOUNDARY-SCAN INSTRUCTION SET ...........................................................................................86
16.3 TAP TEST DATA REGISTERS ......................................................................................................87
16.4 BYPASS REGISTER .....................................................................................................................87
16.5 BOUNDARY-SCAN REGISTER.......................................................................................................87
16.6 TAP CONTROLLER .....................................................................................................................88
17
ELECTRICAL AND TIMING SPECIFICATIONS.........................................................................91
17.1 MAXIMUM RATINGS.....................................................................................................................91
17.2 3.3V DC SPECIFICATIONS ..........................................................................................................91
17.3 3.3V AC SPECIFICATIONS ..........................................................................................................92
17.4 PRIMARY AND SECONDARY BUSES AT 66MHZ CLOCK TIMING ......................................................93
17.5 PRIMARY AND SECONDARY BUSES AT 33MHZ CLOCK TIMING ......................................................93
17.6 POWER CONSUMPTION...............................................................................................................93
18
272-PIN PBGA PACKAGE FIGURE ...........................................................................................94
18.1 PART NUMBER ORDERING INFORMATION.....................................................................................94
APPENDIX A TIMING DIAGRAMS.....................................................................................................A-1
APPENDIX B EVALUATION BOARD USER’S MANUAL..................................................................B-1
PI7C7300 EVALUATION BOARD USER’S MANUAL GENERAL INFORMATION ................................................2
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