參數(shù)資料
型號(hào)： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 78/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
51
06/04/02 Revision 1.07
§
Parity error reported on target bus during posted write transaction (see previous
section)
§
Delayed write data discarded after 2
24 (default) attempts to deliver (224 target
retries received)
§
Delayed read data cannot be transferred from target after 2
24 (default) attempts
(2
24 target retries received)
§
Master timeout on delayed transaction
The device-specific P_SERR# status register reports the reason for the assertion of
P_SERR#. Most of these events have additional device-specific disable bits in the
P_SERR# event disable register that make it possible to mask out P_SERR# assertion
for specific events. The master timeout condition has a SERR# enable bit for that
event in the bridge control register and therefore does not have a device-specific
disable bit.
8
Exclusive Access
This chapter describes the use of the LOCK# signal to implement exclusive access to
a target for transactions that cross PI7C7300.
8.1
Concurrent Locks
The primary and secondary bus lock mechanisms operate concurrently except when
a locked transaction crosses PI7C7300. A primary master can lock a primary target
without affecting the status of the lock on the secondary bus, and vice versa. This
means that a primary master can lock a primary target at the same time that a
secondary master locks a secondary target.
8.2
Acquiring Exclusive Access Across PI7C7300
For any PCI bus, before acquiring access to the LOCK# signal and starting a series of
locked transactions, the initiator must first check that both of the following conditions
are met:
§
The PCI bus must be idle.
§
The LOCK# signal must be de-asserted.
The initiator leaves the LOCK# signal de-asserted during the address phase and
asserts LOCK# one clock cycle later. Once a data transfer is completed from the
target, the target lock has been achieved.
8.2.1
Locked Transactions in Downstream Direction
Locked transactions can cross PI7C7300 only in the downstream direction, from the
primary bus to the secondary bus.
相關(guān)PDF資料
PDF描述
PIC-PROJ2 SOT-23, Rail-to-Rail Output, Picoamp Input Current Precision Op Amp; Package: SOT; No of Pins: 5; Temperature Range: 0°C to +70°C
PIC-TDB PIC TUTOR/DEV BOARD
PIC16C505-20/P 8-BIT, OTPROM, 20 MHz, RISC MICROCONTROLLER, PDIP14
PIC16C54CT-04I/SO 8-BIT, OTPROM, 4 MHz, RISC MICROCONTROLLER, PDSO18
PIC16C56A-20I/JW 8-BIT, UVPROM, 20 MHz, RISC MICROCONTROLLER, CDIP18
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
PI7C8140A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON
PI7C8140AEVB 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評(píng)估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V
PI7C8140AMA 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge
PI7C8140AMAE 功能描述:外圍驅(qū)動(dòng)器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray
PI7C8148A 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。

采購需求

(若只采購一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購

我的聯(lián)系方式

*
*
*