參數(shù)資料
型號： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 106/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
77
06/04/02 Revision 1.07
14.1.36
Secondary Clock Control Register – Offset 68h (continued)
Configuration Register 1 (continued)
15:14
Clock 7 disable
R/W
If either bit is 0, then S1_CLKOUT [7] is enabled.
If both bits are 1, the S1_CLKOUT [7] is disabled.
Configuration Register 2
Bit
Function
Type
Description
1:0
Clock 0 disable
R/W
If either bit is 0, then S2_CLKOUT [0] is enabled.
If both bits are 1, the S2_CLKOUT [0] is disabled.
3:2
Clock 1 disable
R/W
If either bit is 0, then S2_CLKOUT [1] is enabled.
If both bits are 1, the S2_CLKOUT [1] is disabled.
5:4
Clock 2 disable
R/W
If either bit is 0, then S2_CLKOUT [2] is enabled.
If both bits are 1, the S2_CLKOUT [2] is disabled.
7:6
Clock 3 disable
R/W
If either bit is 0, then S2_CLKOUT [3] is enabled.
If both bits are 1, the S2_CLKOUT [3] is disabled.
9:8
Clock 4 disable
R/W
If either bit is 0, then S2_CLKOUT [4] is enabled.
If both bits are 1, the S2_CLKOUT [4] is disabled.
11:10
Clock 5 disable
R/W
If either bit is 0, then S2_CLKOUT [5] is enabled.
If both bits are 1, the S2_CLKOUT [5] is disabled.
13:12
Clock 6 disable
R/W
If either bit is 0, then S2_CLKOUT [6] is enabled.
If both bits are 1, the S2_CLKOUT [6] is disabled.
15:14
Clock 7 disable
R/W
If either bit is 0, then S2_CLKOUT [7] is enabled.
If both bits are 1, the S2_CLKOUT [7] is disabled.
14.1.37
Port Option Register – Offset 74h
Bit
Function
Type
Description
0
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0.
1
Primary MEMR
Command
Alias Enable
R/W
Controls PI7C7300’s detection mechanism for matching
memory read retry cycles from the initiator on the primary
interface
0: exact matching for non-posted memory write retry cycles
from initiator on the primary interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from the initiator on the primary interface
Reset to 0
2
Primary MEMW
Command
Alias Enable
R/W
Controls PI7C7300’s detection mechanism for matching non-
posted memory write retry cycles from the initiator on the
primary interface
0: exact matching for non-posted memory write retry cycles
from initiator on the primary interface
1: alias MEMWI to MEMW for non-posted memory write retry
cycles from initiator on the primary interface
Reset to 0
3
Secondary
MEMR
Command
Alias Enable
R/W
Controls PI7C7300’s detection mechanism for matching
memory read retry cycles from the initiator on S1
0: exact matching for memory read retry cycles from initiator
on the S1 or S2 interface
1: alias MEMRL or MEMRM to MEMR for memory read retry
cycles from initiator on the S1 or S2 interface
Reset to 0
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