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參數(shù)資料
| 型號(hào)： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 60/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
35
06/04/02 Revision 1.07
FFFFh. Note that the initial states of these registers define a memory-mapped
I/O range at the bottom 1MB block of memory. Write these registers with their
appropriate values before setting either the memory enable bit or the master
enable bit in the command register in configuration space.
To turn off the memory-mapped I/O address range, write the memory-mapped I/O
base address register with a value greater than that of the memory-mapped I/O limit
address register.
5.3.2
Prefetchable Memory Base and Limit Address Registers
Locations accessed in the prefetchable memory address range must have true
memory-like behavior and must not exhibit side effects when read. This means that
extra reads to a prefetchable memory location must have no side effects. PI7C7300
pre-fetches for all types of memory read commands in this address space.
The prefetchable memory base address and prefetchable memory limit address
registers define an address range that PI7C7300 uses to determine when to for- ward
memory commands. PI7C7300 forwards a memory transaction from the primary to the
secondary interface if the transaction address falls within the prefetchable memory
address
range.
PI7C7300
ignores
memory
transactions
initiated on the secondary interface that fall into this address range. PI7C7300
does not respond to any transactions that fall outside this address range on the
primary interface and forwards those transactions upstream from the secondary
interface (provided that they do not fall into the memory-mapped I/O range or
are not forwarded by the VGA mechanism).
The prefetchable memory range supports 64-bit addressing and provides additional
registers to define the upper 32 bits of the memory address range, the prefetchable
memory base address upper 32 bits register, and the prefetchable memory limit
address upper 32 bits register. For address comparison, a single address cycle (32-bit
address) prefetchable memory transaction is treated like a 64-bit address transaction
where the upper 32 bits of the address are equal to 0. This upper 32-bit value of 0 is
compared to the prefetchable memory base address upper 32 bits register and the
prefetchable memory limit address upper 32 bits register. The prefetchable memory
base address upper 32 bits register must be 0 to pass any single address cycle
transactions downstream.
Prefetchable memory address range has a granularity and alignment of 1MB.
Maximum memory address range is 4GB when 32-bit addressing is being used.
Prefetchable memory address range is defined by a 16-bit prefetchable memory base
address register at configuration offset 24h and by a 16-bit prefetchable memory limit
address register at offset 26h. The top 12 bits of each of these registers correspond to
bits [31:20] of the memory address. The lowest 4 bits are hardwired to 1h. The lowest
20 bits of the prefetchable memory base address are assumed to be 0 0000h, which
results in a natural alignment to a 1MB boundary. The lowest 20 bits of the
prefetchable memory limit address are assumed to be FFFFFh, which results in an
alignment to the top of a 1MB block.
Note: The initial state of the prefetchable memory base address register is 0000
0000h. The initial state of the prefetchable memory limit address register is 000F
FFFFh. Note that the initial states of these registers define a prefetchable memory
range at the bottom 1MB block of memory. Write these registers with their app-ropriate
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