參數(shù)資料
型號： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 71/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
45
06/04/02 Revision 1.07
For upstream transactions, when the parity error is being passed back from the target
bus and the parity error condition was not originally detected on the initiator bus, the
following events occur:
§
PI7C7300 asserts S_PERR# two cycles after the data transfer, if the following are
both true:
-
The parity error response bit is set in the command register of the primary
interface.
-
The parity error response bit is set in the bridge control register of the
secondary interface.
§
PI7C7300 completes the transaction normally.
7.2.4
Posted Write Transactions
During downstream posted write transactions, when PI7C7300 responds as a target, it
detects a data parity error on the initiator (primary) bus and the following events occur:
§
PI7C7300 asserts P_PERR# two cycles after the data transfer, if the parity error
response bit is set in the command register of primary interface.
§
PI7C7300 sets the parity error detected bit in the status register of the primary
interface.
§
PI7C7300 captures and forwards the bad parity condition to the secondary bus.
§
PI7C7300 completes the transaction normally.
Similarly, during upstream posted write transactions, when PI7C7300 responds as a
target, it detects a data parity error on the initiator (secondary) bus, the following
events occur:
§
PI7C7300 asserts S_PERR# two cycles after the data transfer, if the parity error
response bit is set in the bridge control register of the secondary interface.
§
PI7C7300 sets the parity error detected bit in the status register of the secondary
interface.
§
PI7C7300 captures and forwards the bad parity condition to the primary bus.
§
PI7C7300 completes the transaction normally.
During downstream write transactions, when a data parity error is reported on the
target (secondary) bus by the target’s assertion of S_PERR#, the following events
occur:
§
PI7C7300 sets the data parity detected bit in the status register of secondary
interface, if the parity error response bit is set in the bridge control register of the
secondary interface.
§
PI7C7300 asserts P_SERR# and sets the signaled system error bit in the status
register, if all the following conditions are met:
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