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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 115/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
85
06/04/02 Revision 1.07
and diagnostics. The TAP pins assigned are TCK, TDI, TDO, TMS and TRST#. All
digital input, output, input/output pins are tested except TAP pins and clock pin.
The IEEE 1149.1 Test Logic consists of a TAP controller, an instruction register, and
a group of test data registers including Bypass, Device Identification and Boundary
Scan registers. The TAP controller is a synchronous 16-state machine driven by the
Test Clock (TCK) and the Test Mode Select (TMS) pins. An independent power on
reset circuit is provided to ensure the machine is in TEST_LOGIC_RESET state at
power-up. The JTAG signal lines are not active when the PCI resource is operating
PCI bus cycles.
PI7C7300 implements 3 basic instructions: BYPASS, SAMPLE/PRELOAD, and
EXTEST.
16.1
Boundary Scan Architecture
Boundary-scan test logic consists of a boundary-scan register and support logic.
These are accessed through a Test Access Port (TAP). The TAP provides a simple
serial interface that allows all processor signal pins to be driven and/or sampled,
thereby providing direct control and monitoring of processor pins at the system level.
This mode of operation is valuable for design debugging and fault diagnosis since it
permits examination of connections not normally accessible to the test system. The
following subsections describe the boundary-scan test logic elements: TAP pins,
instruction register, test data registers and TAP controller. Figure 15-1 illustrates how
these pieces fit together to form the JTAG unit.
Figure 16-1. Test Access Port Block Diagram
16.1.1
TAP Pins
The PI7C7300’s TAP pins form a serial port composed of four input connections
(TMS, TCK, TRST# and TDI) and one output connection (TDO). These pins are
described in Table 16-1. The TAP pins provide access to the instruction register and
the test data registers.
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