參數(shù)資料
型號: PI7C7300NA
廠商: PERICOM SEMICONDUCTOR CORP
元件分類: 總線控制器
英文描述: PCI BUS CONTROLLER, PBGA272
封裝: PLASTIC, BGA-272
文件頁數(shù): 37/119頁
文件大?。?/td> 880K
代理商: PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
14
06/04/02 Revision 1.07
TABLE 4-2. WRITE TRANSACTION FORWARDING
Type of Transaction
Type of Forwarding
Memory Write
Posted (except VGA memory)
Memory Write and Invalidate
Posted
Memory Write to VGA memory
Delayed
I/O Write
Delayed
Type 1 Configuration Write
Delayed
4.6.1
Memory Write Transactions
Posted write forwarding is used for “Memory Write” and “Memory Write and Invalidate”
transactions.
When PI7C7300 determines that a memory write transaction is to be forwarded across
the bridge, PI7C7300 asserts DEVSEL# with medium timing and TRDY#
in the next cycle, provided that enough buffer space is available in the posted memory
write queue for the address and at least one DWORD of data. Under
this condition, PI7C7300 accepts write data without obtaining access to the target bus.
The PI7C7300 can accept one DWORD of write data every PCI clock cycle.
That is, no target wait state is inserted. The write data is stored in an internal
posted write buffers and is subsequently delivered to the target.
The PI7C7300 continues to accept write data until one of the following events occurs:
§
The initiator terminates the transaction by de-asserting FRAME# and IRDY#.
§
An internal write address boundary is reached, such as a cache line boundary or
an aligned 4KB boundary, depending on the transaction type.
§
The posted write data buffer fills up.
When one of the last two events occurs, the PI7C7300 returns a target disconnect to
the requesting initiator on this data phase to terminate the transaction.
Once the posted write data moves to the head of the posted data queue, PI7C7300
asserts its request on the target bus. This can occur while PI7C7300 is still receiving
data on the initiator bus. When the grant for the target bus is received and the target
bus is detected in the idle condition, PI7C7300 asserts FRAME# and drives the stored
write address out on the target bus. On the following cycle, PI7C7300 drives the first
DWORD of write data and continues to transfer write data until all write data
corresponding to that transaction is delivered, or until a target termination is received.
As long as write data exists in the queue, PI7C7300 can drive one DWORD of write
data each PCI clock cycle; that is, no master wait states are inserted. If write data is
flowing through PI7C7300 and the initiator stalls, PI7C7300 will signal the last data
phase for the current transaction at the target bus if the queue empties. PI7C7300 will
restart the follow-on transactions if the queue has new data.
PI7C7300 ends the transaction on the target bus when one of the following conditions
is met:
§
All posted write data has been delivered to the target.
§
The target returns a target disconnect or target retry (PI7C7300 starts another
transaction to deliver the rest of the write data).
§
The target returns a target abort (PI7C7300 discards remaining write data).
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