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參數(shù)資料
| 型號(hào)： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 38/119頁(yè) |
| 文件大小： | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
15
06/04/02 Revision 1.07
§
The master latency timer expires, and PI7C7300 no longer has the target bus
grant (PI7C7300 starts another transaction to deliver remaining write data).
Section 4.9.3.2 provides detailed information about how PI7C7300 responds to target
termination during posted write transactions.
4.6.2
Memory Write and Invalidate Transactions
Posted write forwarding is used for Memory Write and Invalidate transactions.
The PI7C7300 disconnects Memory Write and Invalidate commands at aligned cache
line boundaries. The cache line size value in the cache line size register gives the
number of DWORD in a cache line.
If the value in the cache line size register does meet the memory write and invalidate
conditions, the PI7C7300 returns a target disconnect to the initiator either on a cache
line boundary or when the posted write buffer fills.
When the Memory Write and Invalidate transaction is disconnected before a cache line
boundary is reached, typically because the posted write buffer fills, the trans-action is
converted to Memory Write transaction.
4.6.3
Delayed Write Transactions
Delayed write forwarding is used for I/O write transactions and Type 1 configuration
write transactions.
A delayed write transaction guarantees that the actual target response is returned back
to
the
initiator
without
holding
the
initiating
bus
in
wait
states.
A delayed write transaction is limited to a single DWORD data transfer.
When a write transaction is first detected on the initiator bus, and PI7C7300 forwards it
as a delayed transaction, PI7C7300 claims the access by asserting DEVSEL# and
returns a target retry to the initiator. During the address phase, PI7C7300 samples the
bus command, address, and address parity one cycle later. After IRDY# is asserted,
PI7C7300 also samples the first data DWORD, byte enable bits, and data parity. This
information is placed into the delayed transaction queue. The transaction is queued
only if no other existing delayed transactions have the same address and command,
and if the delayed transaction queue is not full. When the delayed write transaction
moves to the head of the delayed transaction queue and all ordering constraints with
posted data are satisfied. The PI7C7300 initiates the transaction on the target bus.
PI7C7300 transfers the write data to the target. If PI7C7300 receives a target retry
in response to the write transaction on the target bus, it continues to repeat the write
transaction until the data transfer is completed, or until an error condition is
encountered.
If PI7C7300 is unable to deliver write data after 2
24 (default) or 232 (maximum)
attempts, PI7C7300 will report a system error. PI7C7300 also asserts P_SERR#
if the primary SERR# enable bit is set in the command register. See Section 7.4 for
information on the assertion of P_SERR#. When the initiator repeats the same write
transaction (same command, address, byte enable bits, and data), and the comp-leted
delayed transaction is at the head of the queue, the PI7C7300 claims the access by
asserting DEVSEL# and returns TRDY# to the initiator, to indicate that the write data
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