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參數(shù)資料
| 型號(hào)： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁(yè)數(shù)： | 39/119頁(yè) |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
16
06/04/02 Revision 1.07
was transferred. If the initiator requests multiple DWORD, PI7C7300 also asserts
STOP# in conjunction with TRDY# to signal a target disconnect. Note that only those
bytes of write data with valid byte enable bits are compared. If any of the byte enable
bits are turned off (driven HIGH), the corresponding byte of write data is not compared.
If the initiator repeats the write transaction before the data has been transferred to the
target, PI7C7300 returns a target retry to the initiator. PI7C7300 continues to return a
target retry to the initiator until write data is delivered to the target, or until an error
condition is encountered. When the write transaction is repeated, PI7C7300 does not
make a new entry into the delayed transaction queue. Section 4.9.3.1 provides detailed
information about how PI7C7300 responds to target termination during delayed write
transactions.
PI7C7300 implements a discard timer that starts counting when the delayed write
completion is at the head of the delayed transaction completion queue.
The initial value of this timer can be set to the retry counter register offset 78h.
If the initiator does not repeat the delayed write transaction before the discard
timer expires, PI7C7300 discards the delayed write completion from the delayed
transaction completion queue. PI7C7300 also conditionally asserts P_SERR#
(see Section 7.4).
4.6.4
Write Transaction Address Boundaries
PI7C7300 imposes internal address boundaries when accepting write data.
The aligned address boundaries are used to prevent PI7C7300 from continuing
a transaction over a device address boundary and to provide an upper limit on
maximum latency. PI7C7300 returns a target disconnect to the initiator when it
reaches the aligned address boundaries under conditions shown in Table 4–3.
TABLE 4-3. WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES
Type of Transaction
Condition
Aligned Address Boundary
Delayed Write
All
Disconnects after one data transfer
Posted Memory Write
Memory write disconnect
control bit = 0
(1)
4KB aligned address boundary
Posted Memory Write
Memory write disconnect
control bit = 1
(1)
Disconnects at cache line boundary
Posted
Memory
Write
and Invalidate
Cache line size
1, 2, 4, 8, 16
4KB aligned address boundary
Posted
Memory
Write
and Invalidate
Cache line size = 1, 2, 4, 8, 16
Cache line boundary if posted
memory write data FIFO does not
have enough space for the cache
line
Note 1. Memory write disconnect control bit is bit 1 of the chip control register at offset 40h in the
configuration space.
4.6.5
Buffering Multiple Write Transactions
PI7C7300 continues to accept posted memory write transactions as long as space for
at least one DWORD of data in the posted write data buffer remains. If the posted
write data buffer fills before the initiator terminates the write transaction, PI7C7300
returns a target disconnect to the initiator.
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