參數(shù)資料
型號(hào)： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 27/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
5
06/04/02 Revision 1.07
3.2
Primary Bus Interface Signals (continued)
Name
Pin #
Type
Description
P_GNT#
U7
PI
Primary Grant (Active LOW).
When asserted,
PI7C7300 can access the primary bus. During idle
and P_GNT# asserted, PI7C7300 will drive P_AD,
P_CBE, and P_PAR to valid logic levels.
P_RESET#
Y5
PI
Primary RESET (Active LOW).
When P_RESET# is active, all PCI signals should
be asynchronously tri-stated.
P_M66EN
V18
PI
Primary Interface 66MHz Operation.
This input is used to specify if PI7C7300 is capable
of running at 66MHz. For 66MHz operation on the
Primary bus, this signal should be pulled “HIGH”.
For 33MHz operation on the Primary bus, this
signal should be pulled “LOW”. In this condition,
S1_M66EN and S2_M66EN will both need to be
“LOW”, forcing both secondary buses to run at
33MHz also.
3.3
Secondary Bus Interface Signals
Name
Pin #
Type
Description
S1_AD[31:0],
S2_AD[31:0]
B20, B19, C20,
C19, C18, D20,
D19, D17, E19,
E18, E17, F20,
F19, F17, G20,
G19, L20, L19,
L18, M20, M19,
M17, N20, N19,
N18, N17, P17,
R20, R19, R18,
T20, T19
J4, H1, H2, H3,
H4, G1, G3, G4,
F2, F3, F4, E1,
E4, D1, C1, B1,
C5, B5, D6, C6,
B6, A6, C7, B7,
D8, C8, D9, C9,
B9, A9, D10,
C10
PB
Secondary Address/Data. Multiplexed address
and data bus. Address is indicated by
S1_FRAME# or S2_FRAME# assertion. Write
data is stable and valid when S1_IRDY# or
S2_IRDY# is asserted and read data is stable and
valid when S1_IRDY# or S2_IRDY# is asserted.
Data is transferred on rising clock edges when both
S1_IRDY# or S2_IRDY# and S1_TRDY# or
S2_TRDY# are asserted. During bus idle,
PI7C7300 drives S1_AD or S2_AD to a valid logic
level when S1_GNT# or S2_GNT# is asserted
respectively.
S1_CBE[3:0],
S2_CBE[3:0]
E20, G18, K17,
P20
F1, A1, A4, A7
PB
Secondary Command/Byte Enables. Multiplexed
command field and byte enable field. During
address phase, the initiator drives the transaction
type on these pins. The initiator then drives the
byte enables during data phases. During bus idle,
PI7C7300 drives S1_CBE[3:0] or S2_CBE[3:0] to a
valid logic level when the internal grant is asserted.
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