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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 81/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
54
06/04/02 Revision 1.07
the command register. Signal SERR# is asserted for the master abort condition if the
master abort mode bit is set in the bridge control register (see Section 7.4).
9
PCI Bus Arbitration
PI7C7300 must arbitrate for use of the primary bus when forwarding upstream
transactions. Also, it must arbitrate for use of the secondary bus when forwarding
downstream transactions. The arbiter for the primary bus resides external to
PI7C7300, typically on the motherboard. For the secondary PCI bus, PI7C7300
implements an internal arbiter. This arbiter can be disabled, and an external arbiter
can be used instead. This chapter describes primary and secondary bus arbitration.
9.1
Primary PCI Bus Arbitration
PI7C7300 implements a request output pin, P_REQ#, and a grant input pin, P_GNT#,
for primary PCI bus arbitration. PI7C7300 asserts P_REQ# when forwarding
transactions upstream; that is, it acts as initiator on the primary PCI bus. As long as at
least one pending transaction resides in the queues in the upstream direction, either
posted write data or delayed transaction requests, PI7C7300 keeps P_REQ# asserted.
However, if a target retry, target disconnect, or a target abort is received in response to
a transaction initiated by PI7C7300 on the primary PCI bus, PI7C7300 de-asserts
P_REQ# for two PCI clock cycles.
For all cycles through the bridge, P_REQ# is not asserted until the transaction request
has been completely queued.
When P_GNT# is asserted LOW by the primary bus arbiter after PI7C7300 has
asserted P_REQ#, PI7C7300 initiates a transaction on the primary bus during the next
PCI clock cycle. When P_GNT# is asserted to PI7C7300 when P_REQ# is not
asserted, PI7C7300 parks P_AD, P_CBE, and P_PAR by driving them to valid logic
levels. When the primary bus is parked at PI7C7300 and PI7C7300 has a transaction
to initiate on the primary bus, PI7C7300 starts the transaction if P_GNT# was asserted
during the previous cycle.
9.2
Secondary PCI Bus Arbitration
PI7C7300 implements an internal secondary PCI bus arbiter. This arbiter supports
eight external masters on secondary 1 and seven external masters on secondary 2
in addition to PI7C7300. The internal arbiter can be disabled, and an external arbiter
can be used instead for secondary bus arbitration.
9.2.1
Secondary Bus Arbitration Using the Internal Arbiter
To use the internal arbiter, the secondary bus arbiter enable pin, S_CFN#, must be
tied LOW. PI7C7300 has eight/seven secondary bus 1/2 request input pins,
S1_REQ#[7:0], S2_REQ#[6:0], and has eight/seven secondary bus 1/2 output grant
pins, S1_GNT#[7:0], S2_GNT#[6:0], to support external secondary bus masters.
The secondary bus request and grant signals are connected internally to the arbiter
and are not brought out to external pins when S_CFN# is HIGH.
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