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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 82/119頁 |
| 文件大?。?/td> | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
55
06/04/02 Revision 1.07
The secondary arbiter supports a 2-sets programmable 2-level rotating algorithm with
each set taking care of 8 requests/ grants. Each set of masters can be assigned to a
high priority group and a low priority group. The low priority group as a whole
represents one entry in the high priority group; that is, if the high priority group consists
of n masters, then in at least every n+1 transactions the highest priority is assigned to
the low priority group. Priority rotates evenly among the low priority group. Therefore,
members of the high priority group can be serviced n transactions out of n+1, while
one member of the low priority group is serviced once every n+1 transactions. Figure
9–1 shows an example of an internal arbiter where four masters, including PI7C7300,
are in the high priority group, and five masters are in the low priority group. Using this
example, if all requests are always asserted, the highest priority rotates among the
masters in the following fashion (high priority members are given in italics, low priority
members, in boldface type): B, m0, m1, m2, m3, B, m0, m1, m2, m4, B, m0, m1, m2,
m5, B, m0, m1, m2, m6, B, m0, m1, m2, m7 and so on.
Figure 9-1. Secondary Arbiter Example
Each bus master, including PI7C7300, can be configured to be in either the low priority
group or the high priority group by setting the corresponding priority bit in the arbiter-
control
register.
The
arbiter-control
register
is
located
at
offset
40h.
Each master has a corresponding bit. If the bit is set to 1, the master is assigned to the
high priority group. If the bit is set to 0, the master is assigned to the low priority group.
If all the masters are assigned to one group, the algorithm defaults to a straight
rotating priority among all the masters. After reset, all external masters are assigned to
the low priority group, and PI7C7300 is assigned to the high priority group. PI7C7300
receives highest priority on the target bus every other transaction, and priority rotates
evenly among the other masters.
Priorities are re-evaluated every time S1_FRAME# or S2_FRAME# is asserted at the
start of each new transaction on the secondary PCI bus. From this point until the time
that the next transaction starts, the arbiter asserts the grant signal corresponding to
the highest priority request that is asserted. If a grant for a particular request is
asserted, and a higher priority request subsequently asserts, the arbiter de-asserts the
asserted grant signal and asserts the grant corresponding to the new higher priority
request on the next PCI clock cycle. When priorities are re-evaluated, the highest
priority is assigned to the next highest priority master relative to the master that
initiated the previous transaction. The master that initiated the last transaction now has
the lowest priority in its group.
If PI7C7300 detects that an initiator has failed to assert S1_FRAME# or S2_FRAME#
after 16 cycles of both grant assertion and a secondary idle bus condition, the arbiter
de-asserts the grant. That master does not receive any more grants until it de-asserts
its request for at least one PCI clock cycle.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
| PI7C8140AMA | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-Port PCI-to-PCI Bridge |
| PI7C8140AMAE | 功能描述:外圍驅動器與原件 - PCI PCI -to -PCI Bridge 2 Port RoHS:否 制造商:PLX Technology 工作電源電壓: 最大工作溫度: 安裝風格:SMD/SMT 封裝 / 箱體:FCBGA-1156 封裝:Tray |
| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
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