參數(shù)資料
型號(hào)： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁(yè)數(shù)： 2/119頁(yè)
文件大小： 880K
代理商： PI7C7300NA
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
x
06/04/02 Revision 1.07
GENERAL INFORMATION (CONTINUED) ......................................................................................................3
FREQUENTLY ASKED QUESTIONS.............................................................................................................4
1.
What is the function of SCAN_EN?............................................................................................4
2.
What is the function of SCAN_TM#?..........................................................................................4
3.
How do you use the external arbiter?.........................................................................................4
4.
What is the purpose of having JP1, JP2, and JP3? ...................................................................4
5.
What is the purpose for having U17, U19, and U20?.................................................................4
6.
How is the evaluation board constructed? .................................................................................4
7.
What is the function of S_CLKIN?..............................................................................................4
8.
What clock frequency combinations does the PI7C7300 support?............................................5
9.
How are the JTAG signals being connected? ............................................................................5
APPENDIX C SCHEMATICS ...............................................................................................................C-2
APPENDIX D ADDRESSES.................................................................................................................D-1
LIST OF TABLES
TABLE 4-1. PCI TRANSACTIONS...................................................................................................... 12
TABLE 4-2. WRITE TRANSACTION FORWARDING .............................................................................. 14
TABLE 4-3. WRITE TRANSACTION DISCONNECT ADDRESS BOUNDARIES ........................................... 16
TABLE 4-4. READ PREFETCH ADDRESS BOUNDARIES....................................................................... 18
TABLE 4-5. READ TRANSACTION PREFETCHING ............................................................................... 18
TABLE 4-6. DEVICE NUMBER TO IDSEL S1_AD OR S2_AD PIN MAPPING........................................ 23
TABLE 4-7. DELAYED WRITE TARGET TERMINATION RESPONSE....................................................... 27
TABLE 4-8. RESPONSE TO POSTED WRITE TARGET TERMINATION.................................................... 28
TABLE 4-9. RESPONSE TO DELAYED READ TARGET TERMINATION.................................................... 29
TABLE 6-1. SUMMARY OF TRANSACTION ORDERING......................................................................... 39
TABLE 7-1. SETTING THE PRIMARY INTERFACE DETECTED PARITY ERROR BIT.................................. 47
TABLE 7-2. SETTING SECONDARY INTERFACE DETECTED PARITY ERROR BIT ................................... 47
TABLE 7-3. SETTING PRIMARY INTERFACE DATA PARITY ERROR BIT ................................................ 48
TABLE 7-4. SETTING SECONDARY INTERFACE DATA PARITY DETECTED BIT ...................................... 48
TABLE 7-5. ASSERTION OF P_PERR#............................................................................................. 49
TABLE 7-6. ASSERTION OF S_PERR#............................................................................................. 49
TABLE 7-7. ASSERTION OF P_SERR# FOR DATA PARITY ERRORS ................................................... 50
TABLE 16-1. TAP PINS................................................................................................................... 86
TABLE 15-2. JTAG BOUNDARY REGISTER ORDER........................................................................... 88
LIST OF FIGURES
FIGURE 9-1. SECONDARY ARBITER EXAMPLE .................................................................................................... 55
FIGURE 16-1. TEST ACCESS PORT BLOCK DIAGRAM ........................................................................................ 85
FIGURE 17-1. PCI SIGNAL TIMING MEASUREMENT CONDITIONS ...................................................................... 92
FIGURE 18.1. 272-PIN PBGA PACKAGE............................................................................................................. 94
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