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參數(shù)資料
| 型號： | PI7C7300NA |
| 廠商： | PERICOM SEMICONDUCTOR CORP |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA272 |
| 封裝： | PLASTIC, BGA-272 |
| 文件頁數(shù)： | 116/119頁 |
| 文件大小： | 880K |
| 代理商： | PI7C7300NA |
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
86
06/04/02 Revision 1.07
16.1.2
Instruction Register
The Instruction Register (IR) holds instruction codes. These codes are shifted in
through the Test Data Input (TDI) pin. The instruction codes are used to select the
specific test operation to be performed and the test data register to be accessed.
The instruction register is a parallel-loadable, master/slave-configured 4-bit wide,
serial-shift register with latched outputs. Data is shifted into and out of the IR serially
through the TDI pin clocked by the rising edge of TCK. The shifted-in instruction
becomes active upon latching from the master stage to the slave stage. At that time
the IR outputs along with the TAP finite state machine outputs are decoded to select
and control the test data register selected by that instruction. Upon latching, all actions
caused by any previous instructions terminate.
The instruction determines the test to be performed, the test data register to be
accessed, or both. The IR is two bits wide. When the IR is selected, the most
significant bit is connected to TDI, and the least significant bit is connected to TDO.
The value presented on the TDI pin is shifted into the IR on each rising edge of TCK.
The TAP controller captures fixed parallel data (1101 binary). When a new instruction
is shifted in through TDI, the value 1101(binary) is always shifted out through TDO,
least significant bit first. This helps identify instructions in a long chain of serial data
from several devices.
Upon activation of the TRST# reset pin, the latched instruction asynchronously
changes to the id code instruction. When the TAP controller moves into the test state
other than by reset activation, the opcode changes as TDI shifts, and becomes active
on the falling edge of TCK.
16.2
Boundary-Scan Instruction Set
The PI7C7300 supports three mandatory boundary-scan instructions (bypass,
sample/preload and extest). The table shown below lists the PI7C7300’s boundary-
scan instruction codes. The “reserved” code should not be used.
Instruction Code
(binary)
Instruction Name
Instruction Code
(binary)
Instruction Name
0000
EXTEST
0101
Reserved
0001
SAMPLE/PRELOAD
1111
Bypass
TABLE 16-1. TAP PINS
Instruction
/
Requisite
Opcode (binary)
Description
Extest
IEEE 1149.1
Required
0000
Extest initiates testing of external circuitry, typically board-
level interconnects and off chip circuitry. Extest connects
the boundary-scan register between TDI and TDO. When
Extest is selected, all output signal pin values are driven by
values shifted into the boundary-scan register and may
change only of the falling edge of TCK. Also, when extest
is selected, all system input pin states must be loaded into
the boundary-scan register on the rising-edge of TCK.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
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| PI7C8140A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2 PORT PCI TO PCI BRIDGE PLX PCI 6140 COMPARISON |
| PI7C8140AEVB | 功能描述:界面開發(fā)工具 2 Port PCI to PCI Bridge Eval Brd RoHS:否 制造商:Bourns 產(chǎn)品:Evaluation Boards 類型:RS-485 工具用于評估:ADM3485E 接口類型:RS-485 工作電源電壓:3.3 V |
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| PI7C8148A | 制造商:PERICOM 制造商全稱:Pericom Semiconductor Corporation 功能描述:2-PORT PCI-TO-PCI BRIDGE ADVANCE INFORMATION |
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