參數(shù)資料
型號(hào)： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 103/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
74
06/04/02 Revision 1.07
14.1.29
Upstream Memory Control Register – Offset 48h
Bit
Function
Type
Description
16
Upstream (S1
or S2 to P)
Memory Base
and Limit
Enable
R/W
0: Upstream memory is the entire range except the down
stream memory channel
1: Upstream memory is confined to upstream Memory Base
and Limit (See offset 50
th and 54th for upstream memory
range)
Reset to 0
17
Upstream (S1
or S2 to P)
Memory
Prefetchable
Enable
R/W
0: Upstream memory is prefetchable at Primary
1: Upstream memory is not prefetchable at Primary
Reset to 0
31:18
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
14.1.30
Hot Swap Switch Time Slot Register – Offset 4Ch
Bit
Function
Type
Description
27:0
Hot Swap Time
Slot
R/W
Hot Swap time slot (15K PCI clocks)
Reset to 0003A98h
30:28
Secondary Bus
Master
Preemption
Control
R/W
Sets the number of clocks for time-to-preempt after another
master request.
000: 32 clocks
001: 8 clocks
010: 16 clocks
011: 64 clocks
100: 128 clocks
Reset to 000
31
Preemption
R/W
Sets preemption.
0: preemption ON
1: preemption OFF
Reset to 0
14.1.31
Upstream (S1 or S2 to P) Memory Base Register – Offset 50h
Bit
Function
Type
Description
3:0
64 bit
addressing
R/O
0: 32 bit addressing
1: 64 bit addressing
Reset to 1
15:4
Upstream
Memory Base
Address
R/W
Controls upstream memory base address.
Reset to 00000000h
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