參數(shù)資料
型號(hào)： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁數(shù)： 36/119頁
文件大?。?/td> 880K
代理商： PI7C7300NA
PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
13
06/04/02 Revision 1.07
4.3
Dual Address Phase
A 64-bit address uses two address phases. The first address phase is denoted by
the asserting edge of FRAME#. The second address phase always follows on the
next clock cycle.
For a 32-bit interface, the first address phase contains dual address command code
on the C/BE#<3:0> lines, and the low 32 address bits on the AD<31:0> lines. The
second address phase consists of the specific memory transaction command code on
the C/BE#<3:0> lines, and the high 32 address bits on the AD<31:0> lines. In this way,
64-bit addressing can be supported on 32-bit PCI buses.
The PCI-to-PCI Bridge Architecture Specification supports the use of dual address
transactions in the prefetchable memory range only. See Section 5.3.2 for a discussion
of prefetchable address space. The PI7C7300 supports dual address transactions in
both the upstream and the downstream direction. The PI7C7300 supports a
programmable 64-bit address range in prefetchable memory for downstream
forwarding of dual address transactions. Dual address transactions falling outside the
prefetchable address range are forwarded upstream, but not downstream. Prefetching
and
posting
are
performed
in
a
manner
consistent
with
the guidelines given in this specification for each type of memory transaction in
prefetchable memory space.
4.4
Device Select (DEVSEL#) Generation
PI7C7300 always performs positive address decoding (medium decode) when
accepting transactions on either the primary or secondary buses. PI7C7300 never
does subtractive decode.
4.5
Data Phase
The address phase of a PCI transaction is followed by one or more data phases.
A data phase is completed when IRDY# and either TRDY# or STOP# are asserted.
A transfer of data occurs only when both IRDY# and TRDY# are asserted during the
same PCI clock cycle. The last data phase of a transaction is indicated when FRAME#
is de-asserted and both TRDY# and IRDY# are asserted, or when IRDY# and STOP#
are asserted. See Section 4.9 for further discussion of transaction termination.
Depending on the command type, PI7C7300 can support multiple data phase
PCI transactions. For detailed descriptions of how PI7C7300 imposes disconnect
boundaries, see Section 4.6.4 for write address boundaries and Section 4.7.3 read
address boundaries.
4.6
Write Transactions
Write transactions are treated as either posted write or delayed write transactions.
Table 4–2 shows the method of forwarding used for each type of write operation.
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