參數(shù)資料
型號(hào)： PI7C7300NA
廠商： PERICOM SEMICONDUCTOR CORP
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA272
封裝： PLASTIC, BGA-272
文件頁(yè)數(shù)： 105/119頁(yè)
文件大?。?/td> 880K
代理商： PI7C7300NA
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PI7C7300
3-PORT PCI-to-PCI BRIDGE
Advanced Information
76
06/04/02 Revision 1.07
14.1.35
P_SERR# Event Disable Register – Offset 64h (continued)
Bit
Function
Type
Description
3
Target Abort
During Posted
Write
R/W
Controls PI7C7300’s ability to assert P_SERR# when it
receives a target abort when attempting to deliver posted write
data.
0: P_SERR# is asserted if this event occurs and the SERR#
enable bit in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
4
Master Abort
On Posted
Write
R/W
Controls PI7C7300’s ability to assert P_SERR# when it
receives a master abort when attempting to deliver posted
write data.
0: P_SERR# is asserted if this event occurs and the SERR#
enable bit in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
5
Delayed Write
Non-Delivery
R/W
Controls PI7C7300’s ability to assert P_SERR# when it is
unable to transfer delayed write data after 2
24 attempts.
0: P_SERR# is asserted if this event occurs and the SERR#
enable bit in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
6
Delayed Read
– No Data
From Target
R/W
Controls PI7C7300’s ability to assert P_SERR# when it is
unable to transfer any read data from the target after 2
24
attempts.
0: P_SERR# is asserted if this event occurs and the SERR#
enable bit in the command register is set
1: P_SERR# is not asserted if this event occurs
Reset to 0
7
Reserved
R/O
Reserved. Returns 0 when read. Reset to 0
14.1.36
Secondary Clock Control Register – Offset 68h
Configuration Register 1
Bit
Function
Type
Description
1:0
Clock 0 disable
R/W
If either bit is 0, then S1_CLKOUT [0] is enabled.
If both bits are 1, the S1_CLKOUT [0] is disabled.
3:2
Clock 1 disable
R/W
If either bit is 0, then S1_CLKOUT [1] is enabled.
If both bits are 1, the S1_CLKOUT [1] is disabled.
5:4
Clock 2 disable
R/W
If either bit is 0, then S1_CLKOUT [2] is enabled.
If both bits are 1, the S1_CLKOUT [2] is disabled.
7:6
Clock 3 disable
R/W
If either bit is 0, then S1_CLKOUT [3] is enabled.
If both bits are 1, the S1_CLKOUT [3] is disabled.
9:8
Clock 4 disable
R/W
If either bit is 0, then S1_CLKOUT [4] is enabled.
If both bits are 1, the S1_CLKOUT [4] is disabled.
11:10
Clock 5 disable
R/W
If either bit is 0, then S1_CLKOUT [5] is enabled.
If both bits are 1, the S1_CLKOUT [5] is disabled.
13:12
Clock 6 disable
R/W
If either bit is 0, then S1_CLKOUT [6] is enabled.
If both bits are 1, the S1_CLKOUT [6] is disabled.
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