參數(shù)資料
型號(hào)： PC8641MSH1333JB
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁(yè)數(shù)： 98/111頁(yè)
文件大?。?/td> 1660K
代理商： PC8641MSH1333JB
87
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
Notes:
1. Caution: The MPX clock to SYSCLK ratio and e600 core to MPX clock ratio settings must be chosen such that the resulting
SYSCLK frequency, e600 (core) frequency, and MPX clock frequency do not exceed their respective maximum or minimum
PLL Ratio” on page 88 for ratio settings.
2. Platform/MPX frequencies between 400 and 500 MHz are not supported.
Note:
1. The Local bus clock speed on LCLK[0:2] is determined by MPX clock divided by the Local Bus PLL ratio programmed in
LCCR[CLKDIV]. See the reference manual for the PC8641D for more information on this.
19.2
MPX to SYSCLK PLL Ratio
The MPX clock is the clock that drives the MPX bus, and is also called the platform clock. The frequency
of the MPX is set using the following reset signals, as shown in Table 19-5:
SYSCLK input signal
Binary value on LA[28:31] at power up
Note that there is no default for this PLL ratio; these signals must be pulled to the desired values. Also
note that the DDR data rate is the determining factor in selecting the MPX bus frequency, since the MPX
frequency must equal the DDR data rate.
Table 19-3.
Platform/MPX Bus Clocking Specifications
Characteristic
Maximum Processor Core Frequency
Unit
Notes
1000, 1250, 1333, 1500 MHz
Min
Max
Platform/MPX bus clock frequency
400
500-600
MHz
Table 19-4.
Local Bus Clocking Specifications
Characteristic
Maximum Processor Core Frequency
Unit
Notes
1000, 1250, 1333, 1500 MHz
Min
Max
Local bus clock speed (for Local Bus
Controller)
25
133
MHz
Table 19-5.
MPX:SYSCLK Ratio
Binary Value of LA[28:31] Signals
MPX:SYSCLK Ratio
0000
Reserved
0001
Reserved
0010
2:1
0011
3:1
0100
4:1
0101
5:1
0110
6:1
0111
Reserved
1000
8:1
1001
9:1
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