參數(shù)資料
型號(hào)： PC8641MSH1333JB
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁(yè)數(shù)： 17/111頁(yè)
文件大?。?/td> 1660K
代理商： PC8641MSH1333JB
13
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
The power dissipation for the PC8641 single core is shown in Table 4-2.
Notes:
1. This is a maximum power supply number which is provided for power supply and board design information. The numbers are
based on 100% bus utilization for each component. The components listed are not expected to have 100% bus usage simul-
taneously for all components. Actual numbers may vary based on activity.
2. Number is based on a per port/interface value.
3. This is based on one eTSEC port used. Since 16-bit FIFO mode involves two ports, the number will need to be multiplied by
two for the total. The other eTSEC protocols dissipate less than this number per port. Note that the power needs to be multi-
plied by the number of ports used for the protocol for the total eTSEC port power dissipation.
4. This includes Local Bus, DUART, JTAG, I2C, DMA, Multiprocessor Interrupts, System Control & Clocking, Debug, Test,
Power management, JTAG and Miscellaneous I/O voltage.
5. These power numbers are for Part Number PC8641xxx1000NX only. V
DD_Coren = 0.95V and VDD_PLAT = 1.05V.
Table 4-2.
PC8641D Individual Supply Maximum Power Dissipation
Component Description
Supply Voltage (Volts)
Power
(Watts)
Notes
Per Core voltage Supply
VDD_Core0/VDD_Core1 = 1.1V at 1500 MHz
21.00
Per Core PLL voltage supply
AV
DD_Core0/AVDD_Core1 = 1.1V at 1500 MHz
0.13
Per Core voltage Supply
V
DD_Core0/VDD_Core1 = 1.05V at 1333 MHz
17.00
Per Core PLL voltage supply
AVDD_Core0/AVDD_Core1 = 1.05V at 1333 MHz
0.13
Per Core voltage Supply
V
DD_Core0/VDD_Core1 = 0.95V at 1000 MHz
11.50
Per Core PLL voltage supply
AV
DD_Core0/AVDD_Core1 = 0.95V at 1000 MHz
0.13
DDR Controller I/O voltage supply
Dn_GVDD = 2.5V at 400 MHz
0.80
Dn_GV
DD = 1.8V at 533 MHz
0.68
Dn_GV
DD = 1.8V at 600 MHz
0.77
16-bit FIFO at 200 MHz eTsec 1&2/3&4 Voltage Supply
L/TVDD = 3.3V
0.11
non-FIFO eTsecnVoltage Supply
L/TV
DD = 3.3V
0.08
x8 SerDes transceiver Supply
SV
DD = 1.1V
0.70
x8 SerDes I/O Supply
XVDD_SRDSn = 1.1V
0.66
SerDes PLL voltage supply Port 1 or 2
AV
DD_SRDS1/AVDD_SRDS2 = 1.1V
0.10
Platform I/O Supply
OV
DD = 3.3V
0.45
Platform source Supply
VDD_PLAT = 1.1V at 600 MHz
12.00
Platform source Supply
V
DD_PLAT = 1.05 Vn at 500 MHz
9.80
Platform source Supply
VDD_PLAT = 1.05 Vn at 400 MHz
7.70
Platform, Local Bus PLL voltage Supply
AVDD_PLAT, AVDD_LB = 1.1V
0.10
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