
98
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
21.4
SerDes Block Power Supply Decoupling Recommendations
The SerDes block requires a clean, tightly regulated source of power (SV
DD and XVDD_SRDSn) to
ensure low jitter on transmit and reliable recovery of data in the receiver. An appropriate decoupling
scheme is outlined below.
Only surface mount technology (SMT) capacitors should be used to minimize inductance. Connections
from all capacitors to power and ground should be done with multiple vias to further reduce inductance.
First, the board should have at least 10 x 10-nF SMT ceramic chip capacitors as close as possible to
the supply balls of the device. Where the board has blind vias, these capacitors should be placed
directly below the chip supply and ground connections. Where the board does not have blind vias,
these capacitors should be placed in a ring around the device as close to the supply and ground
connections as possible.
Second, there should be a 1-F ceramic chip capacitor on each side of the device. This should be
done for all SerDes supplies.
Third, between the device and any SerDes voltage regulator there should be a 10-F, low equivalent
series resistance (ESR) SMT tantalum chip capacitor and a 100-F, low ESR SMT tantalum chip
capacitor. This should be done for all SerDes supplies.
21.5
Connection Recommendations
To ensure reliable operation, it is highly recommended to connect unused inputs to an appropriate signal
level. In general all unused active low inputs should be tied to OV
DD, Dn_GVDD, LVDD, TVDD, VDD_Coren,
and V
DD_PLAT, XVDD_SRDSn, and SVDD as required and unused active high inputs should be con-
nected to GND. All NC (no-connect) signals must remain unconnected.
Special cases:
DDR - If one of the DDR ports is not being used the power supply pins for that port can be connected to
ground so that there is no need to connect the individual unused inputs of that port to ground. Note that
these power supplies can only be powered up again at reset for functionality to occur on the DDR port.
Power supplies for other functional buses should remain powered.
Local Bus - If parity is not used, tie LDP[0:3] to ground via a 4.7 k
Ω resistor, tie LPBSE to OV
DD via a 4.7
k
Ω resistor (pull-up resistor).
SerDes - Receiver lanes configured for PCI Express are allowed to be disconnected (as would occur
when a PCI Express slot is connected but not populated). Directions for terminating the SerDes signals
21.5.1
Guidelines for High-Speed Interface Termination
21.5.1.1
SerDes Interface
The high-speed SerDes interface can be disabled through the POR input cfg_io_ports[0:3] and through
the DEVDISR register in software. If a SerDes port is disabled through the POR input the user can not
enable it through the DEVDISR register in software. However, if a SerDes port is enabled through the
POR input the user can disable it through the DEVDISR register in software. Disabling a SerDes port
through software should be done on a temporary basis. Power is always required for the SerDes inter-
face, even if the port is disabled through either mechanism.
Table 21-1 describes the possible
enabled/disabled scenarios for a SerDes port. The termination recommendations must be followed for
each port.