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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 4/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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101
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
Figure 21-4. Driver Impedance Measurement
Table 21-2 summarizes the signal impedance targets. The driver impedances are targeted at minimum
V
DD, nominal OVDD, 110° C.
Note:
21.8
Configuration Pin Muxing
The PC8641 provides the user with power-on configuration options which can be set through the use of
external pull-up or pull-down resistors of 4.7 k
Ωon certain output pins (see customer visible configuration
pins). These pins are generally used as output only pins in normal operation.
While HRESET is asserted however, these pins are treated as inputs. The value presented on these
pins while HRESET is asserted, is latched when HRESET deasserts, at which time the input receiver is
disabled and the I/O circuit takes on its normal function. Most of these sampled configuration pins are
equipped with an on-chip gated resistor of approximately 20 k
Ω. This value should permit the 4.7-kΩ
resistor to pull the configuration pin to a valid logic low level. The pull-up resistor is enabled only during
HRESET (and for platform /system clocks after HRESET deassertion to ensure capture of the reset
value). When the input receiver is disabled the pull-up is also, thus allowing functional operation of the
pin as an output with minimal signal quality or delay disruption. The default value for all configuration bits
treated this way has been encoded such that a high voltage level puts the device into the default state
and external resistors are needed only when non-default settings are required by the user.
Careful board layout with stubless connections to these pull-down resistors coupled with the large value
of the pull-down resistor should minimize the disruption of signal quality or speed for output pins thus
configured.
The platform PLL ratio and e600 PLL ratio configuration pins are not equipped with these default pull-up
devices.
Table 21-2.
Impedance Characteristics
Impedance
DUART, Control, Configuration,
Power Management
PCI Express
DDR DRAM
Symbol
Unit
R
N
43 Target
25 Target
20 Target
Z
0
W
R
P
43 Target
25 Target
20 Target
Z
0
W
OVDD
OGND
RP
RN
Pad
Data
SW1
SW2
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