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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 90/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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8
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
2. If two separate power supplies are used for V
DD_Core0 and VDD_Core1, they must be at the same nominal voltage and the
individual power supplies must be tracked and kept within 100 mV of each other during normal run time.
3. Caution: Dn_MVIN must meet the overshoot/undershoot requirements for Dn_GVDD as shown in Figure 3-1.
4. Caution: L/TV
IN must meet the overshoot/undershoot requirements for L/TVDD as shown in Figure 3-1 during regular run
time.
5. Caution: OVIN must meet the overshoot/undershoot requirements for OVDD as shown in Figure 3-1 during regular run time.
6. Timing limitations for M,L,T,O)V
7. Applies to a core frequency of 1333 MHz and below.
8. Applies to a core frequency above 1333 MHz.
9. The 2.5V ± 125 mV range is for DDR and 1.8V ± 90 mV range is for DDR2.
10. See Section 9.2 ”FIFO, GMII, MII, TBI, RGMII, RMII, and RTBI AC Timing Specifications” on page 27 for details on the rec-
ommended operating conditions per protocol.
11. The PCI Express interface of the device is expected to receive signals from 0.175 to 1.2V. For more information refer to Sec-
Figure 3-1 shows the undershoot and overshoot voltages at the interfaces of the PC8641.
Figure 3-1.
Overshoot/Undershoot Voltage for Dn_GV
DD/OVDD/LVDD
Note:
1. t
CLK references clocks for various functional blocks as follows:
DDRn = 10% of Dn_MCK period
eTsecn = 10% of ECn_GTX_CLK125 period
Local Bus = 10% of LCLK[0:2] period
SerDes = 10% of SDn_REF_CLK period
I
2C = 10% of SYSCLK
JTAG = 10% of SYSCLK
GND
GND – 0.3V
GND – 0.7V
L/T/D
n_G/O/X/SVDD + 20%
L/T/D
n_G/O/X/SVDD + 5%
VIH
VIL
Not to exceed 10% of tCLK
(1)
L/T/D
n_G/O/S/XVDD
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