參數(shù)資料
型號(hào)： PC8641MSH1333JB
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁(yè)數(shù)： 52/111頁(yè)
文件大?。?/td> 1660K
代理商： PC8641MSH1333JB
45
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
Table 11-3 describes the general timing parameters of the local bus interface at V
DD = 3.3V DC with PLL
disabled.
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tLBIXKH1 symbolizes local bus timing (LB)
for the input (I) to go invalid (X) with respect to the time the tLBK clock reference (K) goes high (H), in this case for clock
one(1). Also, t
LBKHOX symbolizes local bus timing (LB) for the tLBK clock reference (K) to go high (H), with respect to the output
(O) going invalid (X) or output hold time.
2. All timings are in reference to local bus clock for PLL bypass mode. Timings may be negative with respect to the local bus
clock because the actual launch and capture of signals is done with the internal launch/capture clock, which preceeds LCLK
by tLBKHKT.
3. Maximum possible clock skew between a clock LCLK[m] and a relative clock LCLK[n]. Skew measured between comple-
mentary signals at BV
DD/2.
4. All signals are measured from BVDD/2 of the rising edge of local bus clock for PLL bypass mode to 0.4 × BVDD of the signal
in question for 3.3V signaling levels.
5. Input timings are measured at the pin.
6. The value of tLBOTOT is the measurement of the minimum time between the negation of LALE and any change in LAD.
7. For purposes of active/float timing measurements, the Hi-Z or off state is defined to be when the total current delivered
through the component pin is less than or equal to the leakage current specification.
8. Guaranteed by characterization.
Table 11-3.
Local Bus General Timing Parameters: PLL Bypassed
Parameter
Min
Max
Unit
Notes
Local bus cycle time
tLBK
12
–
ns
Local bus duty cycle
t
LBKH/tLBK
45
55
%
Internal launch/capture clock to LCLK delay
tLBKHKT
2.3
3.9
ns
Input setup to local bus clock (except
LUPWAIT)
tLBIVKH1
5.7
–
ps
LUPWAIT input setup to local bus clock
tLBIVKH2
5.6
–
ns
Input hold from local bus clock (except
LUPWAIT)
tLBIXKH1
-1.8
–
ns
LUPWAIT input hold from local bus clock
tLBIXKH2
-1.3
–
ns
LALE output transition to LAD/LDP output
transition (LATCH hold time)
tLBOTOT
1.5
–
ns
Local bus clock to output valid (except
LAD/LDP and LALE)
t
LBKLOV1
–
-0.3
ns
Local bus clock to data valid for LAD/LDP
t
LBKLOV2
–
-0.1
ns
Local bus clock to address valid for LAD
tLBKLOV3
–
0ns
Local bus clock to LALE assertion
t
LBKLOV4
–
0ns
Output hold from local bus clock (except
LAD/LDP and LALE)
t
LBKLOX1
-3.2
–
ns
Output hold from local bus clock for
LAD/LDP
tLBKLOX2
-3.2
–
ns
Local bus clock to output high Impedance
(except LAD/LDP and LALE)
tLBKLOZ1
–
0.2
ns
Local bus clock to output high impedance
for LAD/LDP
t
LBKLOZ2
–
0.2
ns
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