參數(shù)資料
型號(hào)： PC8641MSH1333JB
廠(chǎng)商： E2V TECHNOLOGIES PLC
元件分類(lèi)： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁(yè)數(shù)： 101/111頁(yè)
文件大小： 1660K
代理商： PC8641MSH1333JB
9
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
The PC8641 core voltage must always be provided at nominal V
DD_Coren (See Table 3-2 on page 7 for
actual recommended core voltage). Voltage to the processor interface I/Os are provided through sepa-
rate sets of supply pins and must be provided at the voltages shown in Table 3-2. The input voltage
threshold scales with respect to the associated I/O supply voltage. OV
DD and L/TVDD based receivers are
simple CMOS I/O circuits and satisfy appropriate LVCMOS type specifications. The DDR SDRAM inter-
face uses a single-ended differential receiver referenced to each externally supplied Dn_MV
REF signal
(nominally set to Dn_GV
DD/2) as is appropriate for the (SSTL-18 and SSTL-25) electrical signaling
standards.
3.1.3
Output Driver Characteristics
Table 3-3 provides information on the characteristics of the output driver strengths. The values are pre-
liminary estimates.
Notes:
1. See the DDR Control Driver registers in the PC8641D reference manual for more information.
2. Only the following local bus signals have programmable drive strengths: LALE, LAD[0:31], LDP[0:3], LA[27:31], LCKE,
LCS[1:2], LWE[0:3], LGPL1, LGPL2, LGPL3, LGPL4, LGPL5, LCLK[0:2]. The other local bus signals have a fixed drive
strength of 45
Ω. See the POR Impedance Control register in the PC8641D reference manual for more information about
local bus signals and their drive strength programmability.
3. See Section 18. ”Signal Listings” on page 75 for details on resistor requirements for the calibration of SDn_IMP_CAL_TX
and SDn_IMP_CAL_RX transmit and receive signals.
4. Stub Series Terminated Logic (SSTL-25) type pins.
5. Stub Series Terminated Logic (SSTL-18) type pins.
6. Low Voltage Transistor-Transistor Logic (LVTTL) type pins.
7. Open Drain type pins.
8. Low Voltage Differential Signaling (LVDS) type pins.
9. The drive strength of the DDR interface in half strength mode is at T
J = 105C and at Dn_GVDD (min).
Table 3-3.
Output Drive Capability
Driver Type
Programmable Output
Impedance (
Ω)
Supply Voltage
Notes
DDR1 signal
18
36 (half strength mode)
Dn_GV
DD = 2.5V
DDR2 signal
18
36 (half strength mode)
Dn_GVDD = 1.8V
Local Bus signals
45
25
OV
DD = 3.3V
eTSEC/10/100 signals
45
T/LVDD = 3.3V
30
T/LV
DD = 2.5V
DUART, DMA, Multiprocessor Interrupts, System
Control & Clocking, Debug, Test, JTAG, Power
management, JTAG and Miscellaneous I/O voltage
45
OVDD = 3.3V
I2C150
OVDD = 3.3V
SRIO, PCI Express
100
SVDD = 1.1/1.05V
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