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參數資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數： | 34/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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29
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
Figure 9-2.
FIFO Receive AC Timing Diagram
9.2.2
GMII AC Timing Specifications
This section describes the GMII transmit and receive AC timing specifications.
9.2.2.1
GMII Transmit AC Timing Specifications
Table 9-5 provides the GMII transmit AC timing specifications.
Notes:
1. The symbols used for timing specifications herein follow the pattern t(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t
(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGTKHDV symbolizes GMII transmit timing
(GT) with respect to the tGTX clock reference (K) going to the high state (H) relative to the time date input signals (D) reaching
the valid state (V) to state or setup time. Also, tGTKHDX symbolizes GMII transmit timing (GT) with respect to the tGTX clock ref-
erence (K) going to the high state (H) relative to the time date input signals (D) going invalid (X) or hold time. Note that, in
general, the clock reference symbol representation is based on three letters representing the clock of a particular functional.
For example, the subscript of tGTX represents the GMII(G) transmit (TX) clock. For rise and fall times, the latter convention is
used with the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
Figure 9-3 shows the GMII transmit AC timing diagram.
Figure 9-3.
GMII Transmit AC Timing Diagram
RXD[7:0]
RX_DV
RX_CLK
RX_ER
tFIR
tFIRF
tFIRR
tFIRDV
tFIRDX
Valid data
tFIRH
Table 9-5.
GMII Transmit AC Timing Specifications (At Recommended Operating Conditions with L/TV
DD of 3.3V ± 5%
and 2.5V ± 5%)
Parameter/Condition
Symbol(1)
Min
Typ
Max
Unit
Input low voltage
VIL
––
0.7
V
Input high voltage
V
IH
1.9
––
V
GMII data TXD[7:0], TX_ER, TX_EN setup time
t
GTKHDV
2.5
––
ns
GTX_CLK to GMII data TXD[7:0], TX_ER, TX_EN delay
tGTKHDX
0.5
–
5.0
ns
GTX_CLK data clock rise time (20%-80%)
t
GTXR
––
1.0
ns
GTX_CLK data clock fall time (80%-20%)
tGTXF
––
1.0
ns
TXD[7:0]
TX_EN
GTX_CLK
TX_ER
tGTX
tGTXH
tGTKHDV
tGTKHDX
tGTXF
tGTXR
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