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參數(shù)資料
| 型號(hào)： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類(lèi)： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁(yè)數(shù)： | 8/111頁(yè) |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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105
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
Figure 21-7. JTAG/COP Interface Connection for multiple PC8641 devices in daisy chain configuration
Notes:
1. Populate this with a 10
Ω resistor for short circuit/current-limiting protection.
2. KEY location; pin 14 is not physically present on the COP header.
3. Use a AND gate with sufficient drive strength to drive two inputs.
4. The COP port and target board should be able to independently assert HRESET and TRST to the processor in order to fully
control the processor as shown above.
5. This switch is included as a precaution for BSDL testing. The switch should be open during BSDL testing to avoid acciden-
tally asserting the TRST line. If BSDL testing is not being performed, this switch should be closed or removed.
6. Although pin 12 is defined as a No-Connect, some debug tools may use pin 12 as an additional GND pin for improved signal
integrity.
COP_SRESET
COP_TRST
COP_HRESET
JTAG/COP
SRESET1
SRESET0
TDI
Header
HRESET
TRST
CHKSTP_OUT
CHKSTP_IN
TMS
TCK
TDO
10 k
Ω
10 k
Ω
SRESET1
HRESET
From Target
Board Sources
(if any)
COP_TDI
11
13
3
COP_CHKSTP_OUT
COP_CHKSTP_IN
SRESET1
SRESET0
TDI
TRST
CHKSTP_OUT
CHKSTP_IN
TMS
TCK
TDO
4
15
8
COP_TMS
2
10
COP_TCK
GND
14
9
7
6
NC
COP_VDD_SENSE
16
COP_TDO
1
3
12
2
HRESET
OVDD
SRESET0
4
10 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
10 k
Ω
6
5
10
Ω
PC8641
3
5
NC
1
OVDD
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