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| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 36/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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30
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
9.2.2.2
GMII Receive AC Timing Specifications
Table 9-6 provides the GMII receive AC timing specifications..
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tGRDVKH symbolizes GMII receive timing
(GR) with respect to the time data input signals (D) reaching the valid state (V) relative to the tRX clock reference (K) going to
the high state (H) or setup time. Also, t
GRDXKL symbolizes GMII receive timing (GR) with respect to the time data input signals
(D) went invalid (X) relative to the tGRX clock reference (K) going to the low (L) state or hold time. Note that, in general, the
clock reference symbol representation is based on three letters representing the clock of a particular functional. For exam-
ple, the subscript of t
GRX represents the GMII (G) receive (RX) clock. For rise and fall times, the latter convention is used with
the appropriate letter: R (rise) or F (fall).
2. Guaranteed by design.
Figure 9-4 provides the AC test load for eTSEC.
Figure 9-4.
eTSEC AC Test Load
Figure 9-5 shows the GMII receive AC timing diagram.
Figure 9-5.
GMII Receive AC Timing Diagram
Table 9-6.
GMII Receive AC Timing Specifications (At Recommended Operating Conditions with L/TV
DD of 3.3V ± 5%
and 2.5V ± 5%)
Parameter/Condition
Symbol(1)
Min
Typ
Max
Unit
Input low voltage
VIL
––
0.7
V
Input high voltage
V
IH
1.9
––
V
RX_CLK clock period
t
GRX
–
8.0
–
ns
RX_CLK duty cycle
tGRXH/tGRX
40
–
60
ns
RXD[7:0], RX_DV, RX_ER setup time to RX_CLK
t
GRDVKH
2.0
––
ns
RXD[7:0], RX_DV, RX_ER hold time to RX_CLK
t
GRDXKH
0.5
––
ns
RX_CLK clock rise (20%-80%)
tGRXR
––
1.0
ns
RX_CLK clock fall time (80%-20%)
t
GRXF
1.0
ns
LV
DD/2
Output
Z0 = 50Ω
R
L = 50Ω
RX_CLK
RXD[7:0]
tGRDXKH
tGRX
tGRXH
tGRXR
tGRXF
tGRDVKV
RX_DV
RX_ER
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