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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 46/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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4
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
– Up to 16 Gbytes per memory controller
– Cache line and page interleaving between memory controllers.
Serial RapidIO interface unit
– Supports RapidIO Interconnect Specification, Revision 1.2
– Both 1x and 4x LP-Serial link interfaces
– Transmission rates of 1.25-, 2.5-, and 3.125-Gbaud (data rates of 1.0-, 2.0-, and 2.5-Gbps)
per lane
– RapidIO–compliant message unit
– RapidIO atomic transactions to the memory controller
PCI Express interface
– PCI Express 1.0a compatible
– Supports x1, x2, x4, and x8 link widths
– 2.5 Gbaud, 2.0 Gbps lane
Four enhanced three-speed Ethernet controllers (eTSECs)
– Three-speed support (10/100/1000 Mbps)
– Four IEEE
802.3, 802.3u, 802.3x, 802.3z, 802.3ac, 802.3ab compliant controllers
– Support of the following physical interfaces: MII, RMII, GMII, RGMII, TBI, and RTBI
– Support a full-duplex FIFO mode for high-efficiency ASIC connectivity
– TCP/IP off-load
– Header parsing
– Quality of service support
– VLAN insertion and deletion
– MAC address recognition
– Buffer descriptors are backward compatible with PowerQUICC II and PowerQUICC III
programming models
– RMON statistics support
– MII management interface for control and status
Programmable interrupt controller (PIC)
– Programming model is compliant with the OpenPIC architecture
– Supports 16 programmable interrupt and processor task priority levels
– Supports 12 discrete external interrupts and 48 internal interrupts
– Eight global high resolution timers/counters that can generate interrupts
– Allows processors to interrupt each other with 32b messages
– Support for PCI-Express message-shared interrupts (MSIs)
Local bus controller (LBC)
– Multiplexed 32-bit address and data operating at up to 166 MHz
– Eight chip selects support eight external slaves
Integrated DMA controller
– Four-channel controller
– All channels accessible by both the local and the remote masters
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