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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 66/111頁 |
| 文件大小： | 1660K |
| 代理商： | PC8641MSH1333JB |
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58
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
15.4.2
Transmitter Compliance Eye Diagrams
The TX eye diagram in Figure 15-1 is specified using the passive compliance/test measurement load
(see Figure 15-3 on page 61) in place of any real PCI Express interconnect + RX component.
There are two eye diagrams that must be met for the transmitter. Both eye diagrams must be aligned in
time using the jitter median to locate the center of the eye diagram. The different eye diagrams will differ
in voltage depending whether it is a transition bit or a de-emphasized bit. The exact reduced voltage
level of the de-emphasized bit will always be relative to the transition bit.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
UI.
Note:
It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI inter-
val with a fit algorithm using a minimization merit function (i.e., least squares and median deviation fits).
Figure 15-1. Minimum Transmitter Timing and Voltage Output Compliance Specifications
VRX-DIFF = 0 mV
(D+ D- Crossing Point)
VRX-DIFF = 0 mV
(D+ D- Crossing Point)
(Transition Bit)
VTX-DIFFp-p-MIN = 800 mV
(De-emphasized Bit)
566 mV (3 dB) >= VTX-DIFFp-p-MIN >= 505 mV (4 dB)
.07 UI = UI - 0.3 UI(JTX-TOTAL-MAX)
(Transition Bit)
VTX-DIFFp-p-MIN = 800 mV
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