參數(shù)資料
型號： PC8641MSH1333JB
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁數(shù)： 69/111頁
文件大小： 1660K
代理商： PC8641MSH1333JB
60
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
Notes:
1. No test load is necessarily associated with this value.
2. Specified at the measurement point and measured over any 250 consecutive UIs. The test load in Figure 15-3 on page 61
should be used as the RX device when taking measurements (also refer to the Receiver compliance eye diagram shown in
Figure 15-2 on page 61). If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered
from 3500 consecutive UI must be used as a reference for the eye diagram.
3. A TRX-EYE = 0.40 UI provides for a total sum of 0.60 UI deterministic and random jitter budget for the Transmitter and inter-
connect collected any 250 consecutive UIs. The TRX-EYE-MEDIAN-to-MAX-JITTER specification ensures a jitter
distribution in which the median and the maximum deviation from the median is less than half of the total. UI jitter budget col-
lected over any 250 consecutive TX UIs. It should be noted that the median is not the same as the mean. The jitter median
describes the point in time where the number of jitter points on either side is approximately equal as opposed to the aver-
aged time value. If the clocks to the RX and TX are not derived from the same reference clock, the TX UI recovered from
3500 consecutive UI must be used as the reference for the eye diagram.
4. The Receiver input impedance shall result in a differential return loss greater than or equal to 15 dB with the D+ line biased
to 300 mV and the D- line biased to -300 mV and a common mode return loss greater than or equal to 6 dB (no bias
required) over a frequency range of 50 MHz to 1.25 GHz. This input impedance requirement applies to all valid input levels.
The reference impedance for return loss measurements for is 50
Ω to ground for both the D+ and D- line (that is, as mea-
sured by a Vector Network Analyzer with 50
Ω probes - see Figure 15-3). Note: that the series capacitors CTX is optional for
the return loss measurement.
5. Impedance during all LTSSM states. When transitioning from a Fundamental Reset to Detect (the initial state of the LTSSM)
there is a 5 ms transition time before Receiver termination values must be met on all un-configured Lanes of a Port.
6. The RX DC Common Mode Impedance that exists when no power is present or Fundamental Reset is asserted. This helps
ensure that the Receiver Detect circuit will not falsely assume a Receiver is powered on when it is not. This term must be
measured at 300 mV above the RX ground.
7. It is recommended that the recovered TX UI is calculated using all edges in the 3500 consecutive UI interval with a fit algo-
rithm using a minimization merit function. Least squares and median deviation fits have worked well with experimental and
simulated data.
15.5
Receiver Compliance Eye Diagrams
The RX eye diagram in Figure 15-2 is specified using the passive compliance/test measurement load
(see Figure 15-3) in place of any real PCI Express RX component.
Note:
In general, the minimum Receiver eye diagram measured with the compliance/test measurement load (see
Figure 15-3) will be larger than the minimum Receiver eye diagram measured over a range of systems at
the input Receiver of any real PCI Express component. The degraded eye diagram at the input Receiver is
due to traces internal to the package as well as silicon parasitic characteristics which cause the real PCI
Express component to vary in impedance from the compliance/test measurement load. The input Receiver
eye diagram is implementation specific and is not specified. RX component designer should provide addi-
tional margin to adequately compensate for the degraded minimum Receiver eye diagram (shown in Figure
15-2) expected at the input Receiver based on some adequate combination of system simulations and the
Return Loss measured looking into the RX package and silicon. The RX eye diagram must be aligned in
time using the jitter median to locate the center of the eye diagram.
The eye diagram must be valid for any 250 consecutive UIs.
A recovered TX UI is calculated over 3500 consecutive unit intervals of sample data. The eye diagram is
created using all edges of the 250 consecutive UI in the center of the 3500 UI used for calculating the TX
UI.
Note:
The reference impedance for return loss measurements is 50
Ω to ground for both the D+ and D- line (i.e.,
as measured by a Vector Network Analyzer with 50
Ω probes; see Figure 15-3). Note that the series capac-
itors, CTX, are optional for the return loss measurement.
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