參數(shù)資料
型號(hào)： PC8641MSH1333JB
廠(chǎng)商： E2V TECHNOLOGIES PLC
元件分類(lèi)： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁(yè)數(shù)： 43/111頁(yè)
文件大小： 1660K
代理商： PC8641MSH1333JB
37
0893C–HIREL–01/10
e2v semiconductors SAS 2010
PC8641 and PC8641D [Preliminary]
9.2.7
RMII AC Timing Specifications
This section describes the RMII transmit and receive AC timing specifications.
9.2.7.1
RMII Transmit AC Timing Specifications
The RMII transmit AC timing specifications are in Table 9-13.
Note:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(sig-
nal)(state) (reference)(state) for inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For
example, tMTKHDX symbolizes MII in general, the clock reference symbol representation is based on two
to three letters representing the clock of a particular functional. For example, the subscript of t
MTX repre-
sents the MII(M) transmit (TX) clock. For rise and fall times, the latter convention is used with the
appropriate letter: R (rise) or F (fall).
Figure 9-13 shows the RMII transmit AC timing diagram.
Figure 9-13. RMII Transmit AC Timing Diagram
Table 9-13.
RMII Transmit AC Timing Specifications (At Recommended Operating Conditions with
L/TV
DD of 3.3V ± 5% and 2.5V ± 5%)
Parameter/Condition
Symbol(1)
Min
Typ
Max
Unit
Input low voltage at 3.3 OVDD
VIL
––
0.8
V
Input high voltage at 3.3 OV
DD
V
IH
2.0
–
V
REF_CLK clock period
t
RMT
20.0
ns
REF_CLK duty cycle
tRMTH/tRMT
35
50
65
%
REF_CLK peak-to-peak jitter
t
RMTJ
––
250
ps
Rise time REF_CLK (20%–80%)
t
RMTR
1.0
–
2.0
ns
Fall time REF_CLK (80%–20%)
tRMTF
1.0
–
2.0
ns
REF_CLK to RMII data TXD[1:0], TX_EN delay
t
RMTDX
1
–
10
ns
REF_CLK
TXD[1:0]
tRMTDX
tRMT
tRMTH
tRMTR
tRMTF
TX_EN
TX_ER
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