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參數(shù)資料
| 型號(hào)： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 5/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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102
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
21.9
JTAG Configuration Signals
Correct operation of the JTAG interface requires configuration of a group of system control pins as dem-
onstrated in Figure 21-6 on page 104. Care must be taken to ensure that these pins are maintained at a
valid deasserted state under normal operating conditions as most have asynchronous behavior and spu-
rious assertion will give unpredictable results.
Boundary-scan testing is enabled through the JTAG interface signals. The TRST signal is optional in the
IEEE 1149.1 specification, but is provided on all processors that implement the Power Architecture tech-
nology. The device requires TRST to be asserted during reset conditions to ensure the JTAG boundary
logic does not interfere with normal chip operation. While it is possible to force the TAP controller to the
reset state using only the TCK and TMS signals, more reliable power-on reset performance will be
obtained if the TRST signal is asserted during power-on reset. Because the JTAG interface is also used
for accessing the common on-chip processor (COP) function, simply tying TRST to HRESET is not
practical.
The COP function of these processors allows a remote computer system (typically a PC with dedicated
hardware and debugging software) to access and control the internal operations of the processor. The
COP port connects primarily through the JTAG interface of the processor, with some additional status
monitoring signals. The COP port requires the ability to independently assert HRESET or TRST in order
to fully control the processor. If the target system has independent reset sources, such as voltage moni-
tors, watchdog timers, power supply failures, or push-button switches, then the COP reset signals must
be merged into these signals with logic.
The arrangement shown in Figure 21-5 on page 103 allows the COP port to independently assert
HRESET or TRST, while ensuring that the target can drive HRESET as well.
The COP interface has a standard header, shown in Figure 21-5, for connection to the target system,
and is based on the 0.025" square-post, 0.100" centered header assembly (often called a Berg header).
The connector typically has pin 14 removed as a connector key.
The COP header adds many benefits such as breakpoints, watchpoints, register and memory examina-
tion/modification, and other standard debugger features. An inexpensive option can be to leave the COP
header unpopulated until needed.
There is no standardized way to number the COP header shown in Figure 21-5; consequently, many dif-
ferent pin numbers have been observed from emulator vendors. Some are numbered top-to-bottom then
left-to-right, while others use left-to-right then top-to-bottom, while still others number the pins counter
clockwise from pin 1 (as with an IC). Regardless of the numbering, the signal placement recommended
in Figure 21-5 is common to all known emulators.
For a multi-processor non-daisy chain configuration, Figure 21-6, can be duplicated for each processor.
The recommended daisy chain configuration is shown in Figure 21-7 on page 105. Please consult with
your tool vendor to determine which configuration is supported by their emulator.
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