參數資料
型號： PC8641MSH1333JB
廠商： E2V TECHNOLOGIES PLC
元件分類： 微控制器/微處理器
英文描述： MICROPROCESSOR, CBGA1023
封裝： 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023
文件頁數： 71/111頁
文件大?。?/td> 1660K
代理商： PC8641MSH1333JB
62
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
The long run transmitter specifications use larger voltage swings that are capable of driving signals
across backplanes. This allows a user to drive signals across two connectors and a backplane. The
specifications allow a distance of at least 50 cm at all baud rates.
All unit intervals are specified with a tolerance of ±100 ppm. The worst case frequency difference
between any transmit and receive clock will be 200 ppm.
To ensure interoperability between drivers and receivers of different vendors and technologies, AC cou-
pling at the receiver input must be used.
16.1
DC Requirements for Serial RapidIO SDn_REF_CLK and SDn_REF_CLK
16.2
AC Requirements for Serial RapidIO SDn_REF_CLK and SDn_REF_CLK
Table 16-1 lists AC requirements.
16.3
Signal Definitions
LP-Serial links use differential signaling. This section defines terms used in the description
and specification of differential signals. Figure 16-1 on page 63 shows how the signals are defined. The
figures show waveforms for either a transmitter output (TD and TD) or a receiver input (RD and RD).
Each signal swings between A Volts and B Volts where A > B. Using these waveforms, the definitions
are as follows:
1.
The transmitter output signals and the receiver input signals TD, TD, RD and RD each have a
peak-to-peak swing of A - B Volts.
2.
The differential output signal of the transmitter, V
OD, is defined as VTD-VTD
3.
The differential input signal of the receiver, V
ID, is defined as VRD-VRD
4.
The differential output signal of the transmitter and the differential input signal of the receiver
each range from A - B to -(A - B) Volts.
5.
The peak value of the differential transmitter output signal and the differential receiver input sig-
nal is A - B Volts.
6.
The peak-to-peak value of the differential transmitter output signal and the differential receiver
input signal is 2 * (A - B) Volts.
Table 16-1.
SDn_REF_CLK and SDn_REF_CLK AC Requirements
Symbol
Parameter Description
Min
Typical
Max
Units
Comments
t
REF
REFCLK cycle time
–
10(8)
–
ns
8 ns applies only to serial RapidIO
with 125-MHz reference clock
tREFCJ
REFCLK cycle-to-cycle jitter. Difference
in the period of any two adjacent
REFCLK cycles
––
80
ps
–
t
REFPJ
Phase jitter. Deviation in edge location
with respect to mean edge location
-40
–
40
ps
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