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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 47/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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40
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
Notes:
1. The symbols used for timing specifications herein follow the pattern of t
(first two letters of functional block)(signal)(state) (reference)(state) for
inputs and t(first two letters of functional block)(reference)(state)(signal)(state) for outputs. For example, tMDKHDX symbolizes management data
timing (MD) for the time tMDC from clock reference (K) high (H) until data outputs (D) are invalid (X) or data hold time. Also,
tMDDVKH symbolizes management data timing (MD) with respect to the time data input signals (D) reach the valid state (V)
relative to the tMDC clock reference (K) going to the high (H) state or setup time. For rise and fall times, the latter convention
is used with the appropriate letter: R (rise) or F (fall).
2. This parameter is dependent on the system clock speed. (The maximum frequency is the maximum platform frequency
divided by 64.)
3. This parameter is dependent on the system clock speed. (That is, for a system clock of 267 MHz, the maximum frequency is
8.3 MHz and the minimum frequency is 1.2 MHz; for a system clock of 375 MHz, the maximum frequency is 11.7 MHz and
the minimum frequency is 1.7 MHz).
4. Guaranteed by design.
5. t
MPXCLK is the platform (MPX) clock.
Figure 10-1 provides the AC test load for eTSEC.
Figure 10-1. eTSEC AC Test Load
Note:
Output will see a 50
Ω load since what it sees is the transmission line.
Figure 10-2 shows the MII management AC timing diagram.
Figure 10-2. MII Management Interface Timing Diagram
OV
DD/2
Output
Z0 = 50Ω
R
L = 50Ω
MDC
tMDDXKH
tMDC
tMDCH
tMDCR
tMDCF
tMDDVKH
tMDKHDX
MDIO
(Input)
(Output)
tMDKHDV
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