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參數(shù)資料
| 型號： | PC8641MSH1333JB |
| 廠商： | E2V TECHNOLOGIES PLC |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | MICROPROCESSOR, CBGA1023 |
| 封裝： | 33 X 33 MM, 2.72 MM HEIGHT, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FC-BGA-1023 |
| 文件頁數(shù)： | 77/111頁 |
| 文件大?。?/td> | 1660K |
| 代理商： | PC8641MSH1333JB |
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68
0893C–HIREL–01/10
PC8641 and PC8641D [Preliminary]
e2v semiconductors SAS 2010
Note:
Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The sinuso-
idal jitter may have any amplitude and frequency in the unshaded region of Figure 16-3 on page 69. The sinusoidal jitter
component is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects.
Note:
1. Total jitter is composed of three components, deterministic jitter, random jitter and single frequency sinusoidal jitter. The
sinusoidal jitter may have any amplitude and frequency in the unshaded region of Figure 16-3. The sinusoidal jitter compo-
nent is included to ensure margin for low frequency jitter, wander, noise, crosstalk and other variable system effects
Table 16-10. Receiver AC Timing Specifications: 2.5 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential Input Voltage
V
IN
200
1600
mV p-p
Measured at receiver
Deterministic Jitter Tolerance
JD
0.37
UI p-p
Measured at receiver
Combined Deterministic and
Random Jitter Tolerance
JDR
0.55
UI p-p
Measured at receiver
Total Jitter Tolerance(1)
JT
0.65
UI p-p
Measured at receiver
Multiple Input Skew
SMI
24
ns
Skew at the receiver input
between lanes of a multilane link
Bit Error Rate
BER
10–12
Unit Interval
UI
400
ps
± 100 ppm
Table 16-11. Receiver AC Timing Specifications: 3.125 GBaud
Characteristic
Symbol
Range
Unit
Notes
Min
Max
Differential Input Voltage
V
IN
200
1600
mV p-p
Measured at receiver
Deterministic Jitter Tolerance
JD
0.37
UI p-p
Measured at receiver
Combined Deterministic and
Random Jitter Tolerance
JDR
0.55
UI p-p
Measured at receiver
Total Jitter Tolerance(1)
JT
0.65
UI p-p
Measured at receiver
Multiple Input Skew
SMI
22
ns
Skew at the receiver input
between lanes of a multilane link
Bit Error Rate
BER
10–12
Unit Interval
UI
320
ps
± 100 ppm
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